Introduction

As electronic devices push to faster switching speeds and higher frequencies, PCB designers face greater challenges. Printed circuit boards serving RF, microwave and high-speed digital applications require specialized design practices to ensure signal integrity and avoid unintended radiation.

This article provides an in-depth guide to PCB design for high frequency applications covering:

• PCB materials selection criteria for high frequency
• Component selection and layout considerations
• Routing techniques for high frequency signals
• Smart component placement guidelines
• Critical high speed layout strategies
• Stackup design for high frequency boards
• Modeling and simulation best practices
• Example multi-GHz PCB design walkthrough
• Prototyping and design validation recommendations
• Guidelines for designing testability
• Common high frequency design pitfalls to avoid

By mastering these PCB design principles, electrical engineers can fulfill the exacting demands of cutting-edge wireless, telecom, defense and digital systems operating above GHz frequencies.

PCB Material Selection Considerations

Selecting the optimal PCB substrate is the foundation of any high frequency layout. Key material selection criteria include:

Low Dielectric Constant

• Permits faster signal propagation speed
• Reduces cross-talk between tightly routed traces

Controlled Dielectric Thickness

• Consistent thickness avoids electrical discontinuities
• Thinner dielectrics improve impedance control

Low Loss Tangent

• Reduces signal loss and distortion
• Select materials tested through mmWave frequencies

Tighter Dielectric Tolerances

• Minimizes impedance variability from material variations
• ±5% to ±10% dielectric tolerance common

Thermal Stability

• Maintains stable electrical properties over temperature
• Reduces impedance shifts during operation

Moisture Resistance

• Prevents electrical performance degradation
• Requires materials with low moisture absorption

Advanced PCB materials like Rogers or Taconic RF laminates offer the essential properties needed for designing high frequency PCBs.

Component Selection and Layout

The first step in any successful high frequency PCB layout is component selection and placement planning:

Select Components Rated for High Frequency

• Review datasheets to confirm HF suitability
• Beware of marginal components not fully characterized

Choose Component Packages with Low Inductance and Parasitics

• Avoid long leads
• Favor low-profile SMT packages
• Be mindful of parasitic capacitance

Position Noise-Sensitive Components Judiciously

• Keep away from high-speed lines and interfaces
• Provide shielding if needed

Locate Components for Short Routing

• Place components with high-speed interactions nearby
• Minimize overall trace lengths

Getting the right components in the right locations from the start enables optimum routing.

High Frequency Routing Techniques

With components placed, connecting them demands precision routing:

Impedance Control

• Use impedance calculators to set trace width/spacing
• Account for reference plane proximity
• Maintain consistency across matching nets

Minimize Vias

• Each via adds inductance degrading high frequency response
• Route critical traces on same layer if possible

Eliminate Right Angles

• Use 45° beveled corners instead
• Reduces reflections and ringing

Symmetric Routing

• Match routing for differential pairs
• Controls skew within pair

Shielding

• Enclose critical signals between ground planes
• Adds ground guard traces to isolate noise

Bypass Capacitors

• Sprinkle bypass caps near components
• Suppress noise and transients

Strict adherence to sound routing practices prevents signal degradation.

Component Placement Guidelines

Meticulous component placement is mandatory:

Bypass Capacitors

• Place immediately adjacent to power pins
• Use multiple capacitors for wide frequency range

Decoupling Capacitors

• Surround ICs with interspersed capacitors
• Different values target various frequencies

Voltage Regulators

• Position adjacent to power-hungry ICs
• Minimizes IR drops through board

Crystals and Oscillators

• Locate near IC with short traces
• Adds ground guard traces for isolation

Connectors and Interfaces

• Place at board edge with clear routing paths
• Avoid antennas, sensitive components

EMI Filters

• Insert strategically to dampen emissions
• Often place ahead of connectors

Every component on a high frequency PCB influences signal integrity and must be scrutinized.

Critical High Speed Layout Strategies

In addition to individual routing practices, overarching layout strategies are mandatory:

Partitioning

• Segregate board into zones
• Digital, analog, RF, antenna, high speed areas

Symmetrical Architecture

• Match component placement
• Maintain uniform shape and routing

Short Interconnections

• Keep overall routing compact
• Eliminate excess stubs

Termination

• Strategically terminate lines
• absorbs incident wavefronts

Ground Fill Connectivity

• Maximize ground pour connectivity
• Avoid ground islands

Layer Usage

• Use layers judiciously based on needs
• Transition across layers intelligently

Test Points

• Include coaxial test points
• Facilitate validation and troubleshooting

Every layout technique applied should serve the singular goal of signal integrity.

PCB Stackup Design

For high frequency boards, the layer stackup itself requires special attention:

Thinner Dielectrics

• Enables fine features and lines
• Tighter spacing and impedance control

More Layers

• Permits enclosure of critical nets
• Dedicated power and ground layers
• Low impedance returns beneath traces

Buried and Blind Vias

• Provides isolation between layers
• Avoids stubs from unused vias

Dielectric Selection

• Use consistent dielectric material throughout
• Important for homogenous properties

Differential Routing

• Cores with thicker dielectrics
• Thinner dielectrics above and below
• Centers differential lines for consistency

Embedded Passives

• Integrate capacitance within layers
• Provides localized decoupling

The cross-section design choices ultimately dictate attainable miniaturization and performance.

Modeling and Simulation

Applying modeling and simulation techniques prevents surprises:

** Material Property Simulation**

• Model dielectric constant, loss tangent and characteristics

** Transmission Line Analysis**

• Evaluate losses, reflections, terminations
• Ensure impedance tolerances

** Signal Integrity Modeling**

• Perform circuit, IBIS and 3D EM analysis
• Verify timing, noise margins, eye diagrams

Power Integrity Modeling

• Simulate ground bounce, rail collapse, resonances
• Check voltage levels during transients

EMI/EMC Analysis

• Model emissions and susceptibility
• Assess shielding and external interference

Accurate modeling provides confidence prior to hardware.

Example Multi-GHz PCB Design Walkthrough

Consider a dual channel 10Gbps serial link PCB operating at 6.25 GHz:

Stackup

• 8 layer board with thick cores, thin prepregs
• Differential microstrip lines routed on inner layers

Partitioning

• High-speed digital, power, analog, clocking, power
• Clear separation between zones

Materials

• Low-loss laminate: Rogers RO4350B, εr=3.48
• Low-loss prepreg: Rogers RO4450F, εr=3.23

Routing

• Matched 100 ohm diff pairs + ground traces
• Minimal vias, 45° corners, shielding ground traces

Bypassing

• 100nF caps near each IC power pin
• Smaller high freq. caps interspersed

Termination

• AC-coupled single-ended interconnect
• Source/load termination resistors

Validation

• Time/frequency domain modeling
• Verify eye diagrams, jitter, stability

This example shows how a variety of techniques combine to address high frequency design needs.

Prototyping Recommendations

Given the greater likelihood of issues, prototyping takes on heightened importance:

• Build multiple incremental prototypes
• Incorporate board instrumentation like test points
• Perform careful impedance measurements
• Execute signal integrity testing beyond compliance
• Thermally cycle boards while monitoring performance
• Verify EMI/EMC including radiated emissions
• Be prepared to modify layout based on results
• Allow sufficient time and budget

Thorough prototyping and validation provides confidence prior to release.

Designing for Testability

Special considerations are required to test high frequency designs:

Coaxial Connectors

• Small form factor connectors like SMP or SMA
• Facilitate attaching lab equipment

Test Points

• strategically placed vias or pads
• 0201 package size resistors limit loading

Probe Pads

• Provide access for high frequency probes
• Include ground pads in close proximity

Boundary Scan

• Include test features on ICs
• Verify connectivity and basic function

Built-In Instrumentation

• On-board oscillators, PLLs, counters
• Add monitor nodes and output signals

By planning testability up front in the design process, characterization and troubleshooting is straightforward.

Common High Frequency Design Pitfalls

Despite best efforts, even experienced designers must remain vigilant against some common missteps:

• Selection of inadequate PCB materials
• Failure to provide shielding for sensitive devices
• Incomplete isolation between circuit zones
• Allowing impedance discontinuities
• Poor stackup choices that jeopardize SI
• Excessive vias without impedance control
• Lack of terminating transmission line stubs
• Insufficient decoupling capacitors
• Inadequate consideration of grounding needs
• Forgetting EMI mitigation strategies
• Attempting to route before placement planning

Forewarned is forearmed against these potential pitfalls.

Frequently Asked Questions

Here are some common high frequency PCB design questions:

Q: What are some good stackup guidelines for data rates above 5Gbps?

Use at least 6 layers. Route critical nets on inner layers with thick cores and thin dielectrics. Enclose nets between ground planes. Include 10-20% blank margin border.

Q: How can I estimate appropriate line impedance values?

Use calculators or equations to determine single-ended or differential pair impedances based on dielectric constant, trace dimensions, and reference planes.

Q: What PCB finishes provide the best high frequency signal integrity?

Immersion silver and annealed copper (oxidation resistant) offer minimal skin effect losses at high frequencies.

Q: What are some techniques to reduce crosstalk on densely routed boards?

Shielding ground traces, ground vias near traces, routing orthogonally, wider spacing, lower dielectric constant materials.

Q: When should I avoid vias on a high frequency design?

Minimize vias on clock nets or matched-length nets. Use same-layer jogs instead if possible.

Conclusion

Designing PCBs for multi-GHz applications requires adopting specialized layout practices tailored to the unique needs and challenges. By combining sound high frequency design principles, engineers gain the ability to successfully implement designs operating at the limists of speed and frequency – enabling cutting-edge RF, microwave and high-speed digital systems across countless end applications.

10 Ways for High Frequency PCB Layout

If the frequency of the digital logic circuit reaches or exceeds 45 MHz to 50 MHz, and the circuit operating above this frequency already accounts for a certain amount (for example, 1/3) of the entire electronic system, it is usually called a high frequency circuit. High-frequency circuit design is a very complex design process, and its wiring is critical to the overall design! Master the following ten methods, you will be less detours in high-frequency circuit design.

1. Multi-layer board wiring

High-frequency circuits board tend to have high integration and high wiring density. The use of multi-layer pcb boards is both necessary for wiring and an effective means to reduce interference. In the PCB Layout stage, a reasonable selection of the printed board size of a certain number of layers can make full use of the intermediate layer to set the shielding, better achieve the near grounding, and effectively reduce the parasitic inductance and shorten the transmission length of the signal, and at the same time All of these methods are advantageous for the reliability of high-frequency circuits by reducing the crosstalk of signals and the like.

According to the data, the four-layer board is 20dB lower than the noise of the double-panel. However, there is also a problem. The higher the PCB half-layer number, the more complicated the pcb manufacturing process and the higher the unit cost. This requires us to select the appropriate number of PCB boards for PCB layout. Proper component layout planning and proper routing rules to complete the design.

2. The less the lead bend between the high-speed electronic device pins, the better.

The lead wire of the high-frequency circuit wiring is preferably a full line, which needs to be turned, and can be folded at a 45-degree line or a circular arc. This requirement is only used to improve the fixing strength of the copper foil in the low-frequency circuit, and in the high-frequency circuit, the content is satisfied. One requirement is to reduce the external transmission and mutual coupling of high frequency signals.

3. The shorter the lead between the pins of the high-frequency circuit device, the better.

The radiant intensity of the signal is proportional to the length of the trace of the signal line. The longer the high-frequency signal lead, the easier it is to couple to the component close to it, so for data such as signal clock, crystal, DDR, High-frequency signal lines such as LVDS lines, USB lines, and HDMI lines are required to be as short as possible.

4. The less alternating between the lead layers between the pins of the high-frequency circuit device, the better.

The so-called “the least alternating between the layers of the leads is better” means that the fewer vias (Via) used in the component connection process, the better. According to the side, a via can bring about a distributed capacitance of about 0.5pF, and reducing the number of vias can significantly increase the speed and reduce the possibility of data errors.

5. Pay attention to the “crosstalk” introduced by the parallel lines of the signal lines.

High-frequency circuit wiring should pay attention to the “crosstalk” introduced by the parallel lines of the signal lines. Crosstalk refers to the coupling phenomenon between signal lines that are not directly connected. Since the high-frequency signal is transmitted along the transmission line in the form of electromagnetic waves, the signal line acts as an antenna, and the energy of the electromagnetic field is emitted around the transmission line, and an undesired noise signal generated between the signals due to the mutual coupling of the electromagnetic fields Called Crosstalk.

The parameters of the PCB layer, the spacing of the signal lines, the electrical characteristics of the driver and receiver, and the termination of the signal line all have a certain impact on crosstalk. Therefore, in order to reduce the crosstalk of high-frequency signals, it is required to do the following as much as possible during wiring:

Inserting a ground or ground plane between two lines with severe crosstalk can allow isolation and reduce crosstalk under the conditions allowed by the wiring space.

When there is a time-varying electromagnetic field in the space around the signal line, if parallel distribution cannot be avoided, a large area “ground” can be placed on the reverse side of the parallel signal line to greatly reduce the interference.

Under the premise of wiring space permission, increase the spacing between adjacent signal lines, reduce the parallel length of the signal lines, and the clock lines should be perpendicular to the key signal lines and not parallel.

If the parallel traces in the same layer are almost unavoidable, in the adjacent two layers, the direction of the traces must be perpendicular to each other.

In digital circuits, the usual clock signals are signals with fast edge changes, and the external crosstalk is large. Therefore, in the PCB design, the clock line should be surrounded by ground lines and more ground holes to reduce the distributed capacitance, thus reducing crosstalk.

For the high-frequency signal clock, try to use the low-voltage differential clock signal and cover the ground. You need to pay attention to the integrity of the package.

Do not leave the unused input terminal, but ground it or connect it to the power supply (the power supply is also ground in the high-frequency signal loop). Because the suspended line may be equivalent to the transmitting antenna, grounding can suppress the emission. Practice has proved that using this method to eliminate crosstalk can sometimes be effective immediately.

6. The power supply pin of the integrated circuit block increases the high frequency decoupling capacitor

A high frequency untwisting capacitor is added to the power supply pin of each integrated circuit block. Increasing the high frequency decoupling capacitor of the power supply pin can effectively suppress the high frequency harmonics on the power supply pin to form interference.

7. Ground wire of high frequency digital signal and ground of analog signal are isolated

When analog ground lines, digital ground lines, etc. are connected to the common ground line, high-frequency turbulent magnetic beads should be used to connect or directly isolate and select a suitable place for single-point interconnection. The ground potential of the ground of the high-frequency digital signal is generally inconsistent, and there is often a certain voltage difference between the two directly. Moreover, the ground of the high-frequency digital signal often has a very rich harmonic component of the high-frequency signal. When the digital signal ground and the analog signal ground are directly connected, the harmonics of the high-frequency signal interfere with the analog signal by means of ground-line coupling.

Therefore, in general, the ground of the high-frequency digital signal and the ground of the analog signal are to be isolated, and the method of single-point interconnection at a suitable position or the interconnection of high-frequency turbulent magnetic beads can be adopted.

8. Avoid loops formed by traces

Do not form a loop as much as possible for all types of high-frequency signal traces. If it is unavoidable, make the loop area as small as possible.

9. Must ensure good signal impedance matching

During the transmission of the signal, when the impedance does not match, the signal will reflect in the transmission channel, and the reflection will overshoot the synthesized signal, causing the signal to fluctuate around the logic threshold.

The fundamental way to eliminate the reflection is to make the impedance of the transmitted signal match well. Since the difference between the load impedance and the characteristic impedance of the transmission line is larger, the reflection is also larger. Therefore, the characteristic impedance of the signal transmission line should be equal to the load impedance as much as possible. At the same time, it should be noted that the transmission line on the PCB should not be abrupt or corner, try to keep the impedance of each point of the transmission line continuous, otherwise there will be reflection between the segments of the transmission line. This requires the following wiring rules to be observed when performing high-speed PCB routing:

USB Wiring Rules: USB signal differential routing is required. The line width is 10 mils, the line spacing is 6 mils, and the ground and signal lines are 6 mils apart.

HDMI cabling rules: HDMI signal differential routing is required, linewidth is 10mil, line spacing is 6mil, and the spacing between each pair of HDMI differential signal pairs exceeds 20mil.

The LVDS routing rules require LVDS signal differential traces with a linewidth of 7 mils and a line pitch of 6 mils. The purpose is to control the HDMI differential signal pair impedance to 100+-15% ohm DDR routing rules. The DDR1 routing requires that the signal should not pass through the hole as much as possible. The signal line is equal in width and the line is equidistant from the line. The line must meet the 2W principle to reduce crosstalk between signals. For high-speed devices with DDR2 and above, high-frequency data is required. The lines are equal in length to ensure impedance matching of the signals.

10. Maintain the integrity of signal transmission

Maintain the integrity of signal transmission and prevent “ground bounce” caused by ground segmentation.

As a printed circuit board (PCB) operates, power dissipation in active components raises their junction temperature, transferring heat into conductors and the substrate. Since most PCB materials have low thermal conductivity, this can lead to thermal issues such as hot spots and elevated temperatures. To ensure components remain within their safe operating limits, effective heat dissipation techniques are essential for directing heat away from critical areas.

Thermal management strategies can be categorized as passive or active, both aiming to remove heat from components and disperse it—either into the surrounding air or to cooler regions of the board.

• Passive cooling relies on natural heat transfer mechanisms, such as conduction, convection, and radiation, without requiring additional energy input.
• Active cooling employs more aggressive methods, such as fans, liquid cooling, or thermoelectric coolers, to forcibly dissipate heat.

In many high-power or densely packed PCB designs, a combination of passive and active techniques provides optimal thermal performance. By integrating both approaches, designers can achieve efficient heat dissipation while maintaining reliability.

The Heat Challenge in PCB Design

Heat generation is an inevitable byproduct of electrical current flowing through components on a PCB. While some heat is normal, excessive thermal buildup can lead to numerous problems, including:

1. Reduced component lifespan
2. Decreased overall system reliability
3. Potential circuit malfunctions
4. Thermal stress and physical damage to the PCB

Understanding the impact of heat on PCBs is the first step in developing effective strategies for thermal management.

Innovative Heat Dissipation Strategies for PCBs

To combat the challenges posed by heat in PCB design, engineers and designers have developed a variety of innovative techniques. Let’s explore some of the most effective methods for optimizing heat dissipation in PCBs.

1. Implementing Active Cooling Solutions

One of the most direct approaches to managing heat in PCBs is through the use of active cooling solutions. These methods involve the addition of components specifically designed to remove heat from the system.

Integrating Cooling Fans

Cooling fans are a popular choice for active heat dissipation in PCB designs. They work by creating airflow across the board, which helps to carry away heat generated by components. When implementing cooling fans:

• Consider the placement carefully to maximize airflow across hot spots
• Choose fans with appropriate CFM (cubic feet per minute) ratings for your specific heat load
• Ensure proper mounting to minimize vibration and noise

Incorporating Heat Sinks

Heat sinks are passive components that increase the surface area available for heat dissipation. They are typically made of materials with high thermal conductivity, such as aluminum or copper. To effectively use heat sinks:

• Select heat sinks with appropriate fin designs for your space constraints
• Use high-quality thermal interface materials to ensure good contact with hot components
• Consider combining heat sinks with fans for enhanced cooling performance

2. Optimizing PCB Copper Usage

Copper plays a crucial role in heat dissipation within PCBs due to its excellent thermal conductivity. By strategically utilizing copper in your PCB design, you can significantly improve heat management.

Leveraging Thick Copper Traces

Increasing the thickness of copper traces can enhance their ability to conduct heat away from components. Consider the following when implementing thick copper traces:

• Use wider traces for power and ground connections
• Increase copper weight in areas with high heat generation
• Balance trace thickness with manufacturing constraints and cost considerations

Implementing Copper Planes

Copper planes provide large areas for heat dissipation and can help distribute heat more evenly across the board. To effectively use copper planes:

• Dedicate entire layers to power and ground planes when possible
• Use thermal relief connections to prevent excessive heat sinking during soldering
• Consider split planes to isolate noisy digital circuits from sensitive analog sections

Read more about:

• PCB thermal management
• Thermal Via in PCB
• Battery Thermal Management

3. Exploring Advanced Cooling Technologies

As PCB designs become more complex, advanced cooling technologies are being developed to meet the growing demands of heat dissipation.

Utilizing Heat Pipes

Heat pipes are sealed tubes containing a working fluid that efficiently transfers heat from one location to another. They can be particularly useful in designs where space is limited. When considering heat pipes:

• Evaluate the orientation and length requirements for optimal performance
• Choose appropriate working fluids based on your operating temperature range
• Combine heat pipes with heat sinks or spreaders for enhanced cooling

Implementing Liquid Cooling Systems

For high-power applications, liquid cooling systems can offer superior heat dissipation compared to air-based methods. While more complex to implement, they can provide significant thermal management benefits:

• Consider closed-loop systems for easier maintenance and reduced risk of leaks
• Select appropriate coolants based on thermal properties and compatibility with materials
• Design the system to minimize the risk of electrical shorts in case of leaks

Material Selection for Enhanced Thermal Management

The choice of materials used in PCB construction plays a critical role in heat dissipation. By selecting the right materials, you can significantly improve the thermal performance of your PCB design.

Substrate Materials: Balancing Performance and Cost

The substrate material forms the foundation of the PCB and greatly influences its thermal characteristics. Common options include:

1. FR-4: Standard and cost-effective, but with limited thermal conductivity
2. Aluminum PCBs: Excellent thermal conductivity, ideal for LED applications
3. Ceramic substrates: High thermal conductivity, suitable for high-frequency applications
4. Polyimide: Good for flexible PCBs with moderate thermal requirements

When selecting substrate materials, consider:

• The thermal conductivity required for your application
• Cost constraints and production volume
• Electrical properties such as dielectric constant and loss tangent
• Mechanical properties like flexibility and dimensional stability

Thermal Interface Materials: Bridging the Gap

Thermal interface materials (TIMs) are crucial for ensuring efficient heat transfer between components and heat sinks or other cooling solutions. Popular TIMs include:

• Thermal greases
• Phase change materials
• Thermal pads
• Thermally conductive adhesives

When choosing TIMs, consider factors such as:

• Thermal conductivity
• Ease of application and rework
• Long-term stability and reliability
• Compatibility with your assembly process

Thermal Management Techniques for Compact PCB Designs

As electronic devices continue to shrink in size, managing heat dissipation in compact PCB designs becomes increasingly challenging. Here are some strategies to improve thermal performance in space-constrained designs:

Optimizing Component Placement

Careful component placement can significantly impact heat distribution across the board:

• Group high-heat components together and place them near the board’s edges
• Use thermal simulations to identify and address potential hot spots
• Consider the impact of component placement on airflow patterns

Leveraging Thermal Via Arrays

Thermal vias are plated through-holes that help conduct heat between PCB layers. To effectively use thermal via arrays:

• Place them directly under or around hot components
• Use a grid pattern to maximize heat transfer
• Fill vias with thermally conductive materials for enhanced performance

Implementing Copper Coin Technology

Copper coins are thick pieces of copper inserted into the PCB to provide localized heat spreading. This technique can be particularly effective for managing heat from high-power components in compact designs:

• Use copper coins under components with high thermal output
• Ensure proper integration with the PCB manufacturing process
• Consider combining copper coins with other cooling techniques for optimal results

Heat Dissipation in Flexible PCB Designs

Flexible PCBs present unique challenges for heat dissipation due to their thin and bendable nature. However, several strategies can be employed to manage thermal issues in flex circuits:

Material Selection for Flex PCBs

Choose materials that balance flexibility with thermal performance:

• Polyimide-based substrates offer good thermal stability
• Consider hybrid designs with rigid sections for improved heat dissipation
• Use thermally conductive adhesives for bonding layers

Implementing Copper Patterns

Strategic use of copper can enhance heat dissipation in flex circuits:

• Utilize copper planes where possible, especially in areas with high heat generation
• Consider hatched ground planes to maintain flexibility while improving thermal performance
• Use thicker copper weights in critical areas, balancing thermal needs with flexibility requirements

Incorporating Thermal Management Layers

For applications with higher thermal demands, consider adding dedicated thermal management layers:

• Integrate heat-spreading materials like graphite or aluminum
• Use thermally conductive but electrically insulating materials to maintain signal integrity
• Design thermal layers to work in conjunction with the circuit’s bending requirements

Conclusion: A Holistic Approach to PCB Heat Dissipation

Effective heat dissipation in PCB design requires a comprehensive approach that considers various factors, including:

1. Component selection and placement
2. Material choices for substrates and thermal interfaces
3. Implementation of active and passive cooling solutions
4. Optimization of copper usage and layout design
5. Utilization of advanced thermal management techniques

By carefully considering these aspects and implementing appropriate strategies, designers can create PCBs that effectively manage heat, ensuring optimal performance and longevity of electronic devices. As technology continues to advance, staying informed about the latest developments in thermal management techniques and materials will be crucial for creating efficient and reliable PCB designs.

Remember, the key to successful heat dissipation in PCB design lies in finding the right balance between thermal performance, cost-effectiveness, and manufacturing feasibility. By adopting a holistic approach and leveraging the techniques discussed in this article, you can optimize your PCB designs for superior heat dissipation and overall performance.

Introduction

Decoupling and bypass capacitors are two of the most ubiquitous and important passive components used on printed circuit boards. They serve crucial functions in providing stable voltage regulation, filtering noise, and ensuring proper device operation.

While the terms “decoupling capacitor” and “bypass capacitor” are sometimes used interchangeably, there are in fact important distinctions between the two. Understanding the differences allows engineers to make informed design decisions when selecting and placing these capacitors.

This article provides an in-depth look at decoupling and bypass caps including:

• The functions and purposes of each type
• Key differences in behavior and characteristics
• Guidelines for selecting the proper capacitance and type
• Optimal placement considerations
• Modeling and simulating decoupling performance
• Mitigating decoupling issues like parallel and series resonance
• Real-world decoupling design examples
• Summary comparison of decoupling versus bypass caps

Read on to learn how proper utilization of decoupling and bypass capacitors can optimize circuit performance and prevent difficult-to-diagnose stability issues.

Functions of a Decoupling Capacitor

Decoupling capacitors, also known as bypass capacitors, serve several vital functions:

1. Maintain Steady Voltage to ICs

• During operation, ICs can draw current in abrupt spikes and surges
• This leads to fluctuations and noise on the DC power supply rails
• Decoupling caps maintain a stable voltage by supplying current to the IC during demand spikes
• They recharge quickly between spikes to remain ready for the next demand

2. Filter Noise

• Switching noise is generated on power rails due to digital logic transitions
• High frequency noise can impair circuit operation
• Decoupling caps filter noise through low impedance across a wide frequency spectrum

3. Reduce Ground Bounce

• Sudden current draw can cause ground potential to bounce or skew
• Capacitors between ground pins dampen bounce and skew
• This maintains signal integrity and noise margins

4. Control Impedances

• Decoupling caps help control impedances along power distribution network
• This avoids impedance discontinuities which reflect noise
• Proper impedance helps signals propagate without distortion

In essence, decoupling capacitors act like small localized energy reservoirs to supply current, filter noise, and maintain stable voltage to enable proper functioning of nearby ICs and devices. Next, we’ll see how bypass capacitors serve some similar but also differing functions.

Functions of a Bypass Capacitor

While bypass capacitors provide some similar functions as decoupling caps, key differences include:

1. Differential Noise Rejection

• Unlike decoupling caps directly from VDD to ground, bypass caps are placed in series from signal to ground
• This attenuates common-mode noise while allowing the signal to pass
• Useful for signals prone to picking up external interference

2. Band-Selective Filtering

• Proper bypass cap selection targets filtering of specific noise frequencies
• Values are chosen based on the frequency content to be rejected
• Provides more selective filtering compared to broadband decoupling caps

3. Cross-Talk Reduction

• In sensitive high-speed data links, capacitance between signal pairs reduces coupling
• Prevents signals from influencing one another
• Helps meet tighter timing margins at high data rates

4. Impedance Tuning

• Unlike decoupling caps from VDD to ground, bypass caps are in series with signals
• Can help fine tune characteristic impedance in transmission lines
• Allows better impedance matching through the signal chain

In summary, while decoupling caps focus primarily on power integrity, bypass capacitors address signal integrity objectives. With the functions covered, let’s compare some key characteristics.

Key Characteristic Differences Between Decoupling and Bypass Caps

While there is some overlap in functions, several key characteristic differences help distinguish decoupling and bypass capacitors:

Characteristic	Decoupling Capacitor	Bypass Capacitor
Location	Close proximity between power and ground pins	In series between signal and ground
Purpose	Maintain steady voltage and filter power rail noise	Attenuate noise on signals and reduce cross-talk
Capacitance	High capacitance, small case sizes	Lower capacitance based on frequency response needs
Performance	Low ESR and impedance over wide frequency range	Targeted frequency response characteristics
Types	Ceramic, polymer, tantalum, niobium	Ceramic, film, mica, polystyrene
Packaging	Surface mount chips, leaded disks	Surface mount monolithic and stacked chips

Some key points:

• Decoupling caps are placed close to IC power pins with short connections
• Bypass caps are placed along signal paths, often near terminals
• Decoupling caps need high capacitance in small sizes
• Bypass caps focus on targeted frequency performance

Now let’s look at selecting appropriate capacitance values for the different applications.

Selecting Capacitance Value

The target capacitance value depends greatly on whether the capacitor will serve a decoupling or bypass function:

Decoupling Capacitors

• Higher capacitance provides greater charge storage and noise filtering
• Target mounting inductance limits useable capacitance
• Typical sizes from 100nF to 10uF
• 0.1uF, 0.47uF and 1uF most common

Bypass Capacitors

• Chosen based on frequency response needed
• Lower values for higher frequencies, higher for lower frequencies
• 10nF to 100nF common for high speed serial links
• 0.001uF to 0.1uF typical for operational amplifier power pins

Here are some guidelines for selecting decoupling capacitance:

1. Determine Charge Requirements

• Estimate instantaneous charge needed during voltage spikes
• Factors: chip size, power draw, activity level
• More decoupling capacitance required for larger, more active ICs

2. Consider Distance to Power Supply

• Further distance to power source requires more local charge reservoir
• Increase decoupling caps for boards with single centralized regulator

3. Analyze Transient Loading

• Circuits with larger instantaneous current spikes need bigger decoupling caps
• Examine current draw waveform to determine worst-case transients

4. Factor in Inductance

• Total inductance to capacitor limits high frequency performance
• More capacitance can help compensate for higher inductance

With bypass capacitors, it is more important to select the proper capacitor technology for the desired frequency response. We’ll look more at passive component technologies later on.

Placement Considerations

Optimal placement is critical to maximize decoupling and bypass capacitor effectiveness.

Decoupling Capacitors

• Place immediately adjacent to power pins to minimize loop inductance
• Often locate multiple decoupling caps in parallel
• Position between IC and next decoupling cap in the distribution network

Bypass Capacitors

• Mount as close to the signal entry/exit point as possible
• Minimize distance between bypass cap and signal plane
• Place between signal source and noisy nodes

Some high performance PCB layout techniques include:

• Embedded decoupling caps within the inner layers
• Interdigitated capacitor arrays surrounding the IC
• 3D capacitor stacks combining multiple height values
• Periodic distribution of decoupling caps in grid patterns

Careful placement is key to realizing the full performance of both decoupling and bypass capacitors in the circuit.

Modeling and Simulating Decoupling

To analyze decoupling effectiveness, models are needed to simulate the PDN impedance behavior. Some approaches include:

IC Model

• Simple model: Current source, resistor, and inductor
• More complex: Resistor-capacitor (RC) network models IC and package
• Determines current load used to stress the PDN

PDN Model

• Capacitors, mounting inductance, plane impedance
• Vias, power and ground planes, interconnects
• Capture frequency-dependent impedance

Simulation Approaches

• SPICE circuit simulations
• Electromagnetic solvers for planes and components
• Specialized PDN impedance solvers
• IBM Power Delivery Network Analysis (PDNA) methodology

Simulations help predict resonances, identify insufficient decoupling, and determine impacts of board changes prior to a PCB layout. This enables proactive optimization of the decoupling network.

Mitigating PDN Impedances Issues

Decoupling capacitors help control PDN impedances, but potential issues must be addressed:

Parallel Resonance

• Caused by capacitors and voltage plane inductance
• Leads to unintended impedance peaks
• Mitigate by reducing loop inductance and/or increasing capacitance

Series Resonance

• Caused by capacitors and voltage plane capacitance
• Causes unwanted impedance nulls
• Mitigate by reducing plane capacitance and/or inductance

Spreading Inductance

• Currents spread non-uniformly in planes causing varying inductance
• Manage by proper decoupling placement, via distribution, and ground pours

Insufficient Decoupling

• Too little capacitance fails to supply transient current loads
• Add more decoupling caps near problem area
• Increase capacitance and reduce mounting inductance

Thorough PDN planning, simulation, and design reviews help identify and resolve decoupling issues before manufacturing the PCB.

Real-World Decoupling Capacitor Design Examples

Here are some examples highlighting decoupling design and optimization for different applications:

1. High-Speed Memory Interface

• DDR5 interface with memory controller IC
• High transient currents and noise at >5GHz speeds
• Target impedance below 0.5 ohm up to 5GHz
• Employed Pi-filter decoupling with two parallel 100nF MLCC caps and ferrite bead
• Used interdigitated capacitors adjacent to IC with ground vias in grid pattern

2. Automotive RADAR PCB

• 24 GHz MMIC (monolithic microwave IC) RF transceiver
• Extremely low supply noise required for phase coherence
• Leveraged embedded distributed capacitance below ICs
• Surrounded MMIC with multi-density stack of capacitors: 4x10nF, 2x100nF, 10uF tantalum
• Extensive power plane copper fills to reduce spreading inductance

3. High Power GPU

• High current transient loads up to 150A
• Target impedance below 5mohm up to 100MHz
• Employed land-side capacitors with bottom-side ground vias
• Grid of 4x1000uF POSCAP tantalum bulk capacitors
• 20x10uF ceramic capacitors distributed around processor

These examples showcase real-world applications of effective decoupling design techniques tailored to the specific requirements.

Comparison Summary: Decoupling vs. Bypass Capacitors

Here is a summary overview of the key differences between decoupling and bypass capacitors:

Parameter	Decoupling Capacitor	Bypass Capacitor
Location	Near IC power pins	Along signal path
Purpose	Stable voltage, filter noise	Attenuate signal interference
Capacitance Value	Higher, depends on IC current demand	Lower, based on frequency response
Performance	Low impedance over wide frequency band	Targeted filtering for noise frequencies
Types	Ceramic, polymer, electrolytic	Ceramic, film, mica
Packaging	Surface mount, through-hole	Monolithic and stacked surface mount
Resonances	Mitigate parallel and series resonance	Less susceptible
Modeling	PDN impedance, IC transient loads	Source and load termination

This summarizes some of the key differences in a concise comparison table. Both capacitor types are critical PCB components but address distinct requirements.

Frequently Asked Questions

Here are some common FAQs regarding decoupling and bypass capacitors:

Q: Can a bypass capacitor be used for decoupling and vice versa?

In some cases yes, but performance may be compromised compared to using the optimal type. The distinguishing factors are location relative to power vs. signal pins and wide-band vs. selective frequency response characteristics.

Q: How are bypass/decoupling capacitors modeled in circuit simulation?

Decoupling caps are modeled as part of the full PDN with emphasis on equivalent series inductance. Bypass caps can be modeled as simple capacitive sources with appropriate frequency-dependent impedance characteristics.

Q: What testing is done to characterize decoupling capacitor performance?

Parameters like equivalent series resistance/inductance and impedance versus frequency may be tested to characterize decoupling effectiveness across operating frequency ranges.

Q: How can I calculate the target impedance for my PDN?

Factors like anticipated load transient current, switching noise tolerance, and voltage margin are used to estimate the maximum allowable PDN impedance based on voltage deviation limits.

Q: What construction techniques help reduce inductance?

Shorter traces, interdigitated capacitors, embedded capacitance, and vias in tight grid patterns all help minimize mounting loop inductance.

Conclusion

Decoupling and bypass capacitors address unique but equally vital functions in maintaining proper circuit operation. As PCBs continue advancing to faster speeds and lower voltages, utilizing the appropriate capacitor technologies and design techniques is imperative. Understanding the key distinctions between decoupling and bypass caps will enable engineers to make informed design decisions.

The detailed comparisons and examples in this article equip PCB designers with deep knowledge to deploy decoupling and bypass capacitors effectively. By leveraging the right capacitor solutions tailored to each application’s specific needs, robust performance and stability can be achieved.

Introduction

Clock signals are essential timing references used to synchronize and coordinate the operation of digital logic circuits in integrated circuits and electronics systems. A clock waveform oscillates between a high and low logic level at a regular frequency. The transition edges trigger sequential logic state changes and digital computations. Clock signals must exhibit precise frequencies with low jitter and high spectral purity for reliable circuit operation.

Various clock generation circuits are available to produce different frequencies using crystal, relaxation, ring, and phase-locked loop oscillators along with frequency multipliers and dividers. Selecting the right approach depends on frequency stability, jitter, power and tuning range requirements. This article provides an overview of commonly used clock generation circuits highlighting their operating principles, characteristics, and applications.

Clock Signal Properties

Desirable attributes of stable clock signals are:

• Accurate oscillation frequency matching system specifications
• Low cycle-to-cycle jitter to precisely trigger logic
• High spectral purity with minimal harmonics
• Square waveform with fast rise and fall times
• Constant peak-to-peak voltage amplitude
• Low duty cycle distortion
• High signal integrity over chip/board distribution

Crystal Oscillator

This uses the mechanical resonance of a vibrating crystal to generate a sinusoidal signal at a precise natural frequency determined by the crystal cut and dimensions. Feedback amplifiers sustain the oscillations applying bias voltages and limiting gain to overcome losses. Output buffers provide squared CMOS/TTL compatible clock outputs.

Characteristics

• Excellent frequency stability and accuracy
• Low jitter (<100 ps)
• High spectral purity
• Frequency range from kHz to MHz

Applications

• Primary system reference clocks
• Real-time clocks
• RF systems
• Instrumentation

Relaxation Oscillator

Here an RC network is repetitively charged and discharged between two voltage thresholds to produce a timing clock signal. Comparators switch the output state when the RC voltage crosses the thresholds.

Characteristics

• No external components
• Moderate accuracy and stability
• Higher jitter
• High power consumption

Applications

• Embedded microcontroller clocks
• Timer circuits
• Low-frequency clock generation

Ring Oscillator

This consists of an odd number of inverting logic gates connected in a circular chain. The output of the last gate is fed back to the input of the first, causing oscillations at a frequency determined by the gate delays. Buffers provide synchronized outputs.

Characteristics

• Completely on-chip integration
• Tunable frequency by control voltage
• Moderate jitter
• Noisy output requiring filtering

Applications

• On-chip clock generation
• Analog-to-digital converters
• Frequency synthesis in PLLs
• Random number generation

Phase Locked Loop (PLL)

A PLL synchronizes its oscillator output to match either an external reference clock or crystal oscillator using a feedback control loop. The phase detector generates error voltages proportional to phase differences driving the oscillator frequency toward zero phase error.

Characteristics

• Excellent frequency stability when locked
• Very low jitter

-Tunable frequency multiplication/division

• Integrated implementations

Applications

• Microprocessor/communication IC clocks
• Frequency synthesis of various clock rates
• Clock recovery from data communications
• Frequency modulation/demodulation

Clock Conditioning Circuits

Supplementary circuits help provide final clock signals with desired characteristics:

Frequency Multipliers

Use analog or digital techniques to generate harmonic multiples of an input reference frequency. Popular for sub-clock generation.

Dividers

Divide input clock frequencies down digitally to lower clock rates using ripple counters or synchronous counters.

Buffers

Provide periodic clock signal refreshment, fanning-out, and amplitude limiting to safely drive large clock distribution loads.

Filters

Remove noise and harmonics to improve spectral purity using LC and RC low-pass filters.

Clock Distribution

The generated clock is distributed to various logic blocks using balanced trees and grid networks overlaid on chip or board along with careful impedance control, termination and buffering to control reflections and skew.

Choosing Clock Generation Circuits

The table below summarizes the key selection criteria:

Parameter	Crystal Oscillator	RC Oscillator	Ring Oscillator	PLL
Frequency Stability	Excellent	Poor	Moderate	Excellent (with reference)
Frequency Tunability	Fixed	Limited	Excellent	Excellent
Jitter	Very low	High	Moderate	Very low
Spectral Purity	Excellent	Moderate	Poor (spurs)	Excellent
Integration Level	External	Medium	High	High
Power Consumption	Low	High	Medium	Medium

Conclusion

A wide variety of clock generation circuits provide multiple options to engineers designing digital systems, based on requirements like operating frequency, jitter tolerance, tunability, cost and power constraints. Proper selection coupled with robust distribution network design delivers stable synchronized timing signals vital for reliable functioning of synchronous logic circuits. Given their criticality, clocking circuits and techniques continue to be an area of innovation to support advancing chip technologies and faster computing systems.

Frequently Asked Questions (FQA)

Q1: Why is using a crystal oscillator better than an LC tank oscillator for clock generation?

A1: The precise resonant frequency of quartz crystals gives extremely stable and accurate clock signals in comparison to LC tank circuits which are susceptible to drift with temperature and component variations.

Q2: What techniques can be used to reduce clock jitter from oscillators?

A2: Using higher Q-factor crystals/LC tanks, providing sufficient loop gain in oscillator feedback paths, maintaining well-regulated bias voltages, filtering noise sources, and buffering clock signals before distribution help minimize jitter.

Q3: How does a phase-locked loop provide tunable clock generation?

A3: The voltage-controlled oscillator inside the PLL allows its output clock frequency to be tuned across a range determined by the VCO transfer characteristic. The PLL locks the VCO to an accurate reference input clock.

Q4: Why is clock signal integrity important in digital systems?

A4: Clean clocks with balanced rise/fall times, constant amplitude and shape are critical for synchronous digital logic. Noise, reflections, jitter degrade switching performance and computation reliability.

Q5: How can multiple clock frequencies be generated from a single reference source?

A5: Using a frequency divider produces integer sub-multiples of the source frequency. Frequency multipliers and mixers generate harmonic multiples. PLLs allow both integer scaling and arbitrary frequency synthesis.

Introduction

Soldermask or solder resist is the protective layer of polymer coating applied over the copper traces on printed circuit boards (PCBs) to control solder spreading and prevent bridging between pads during component assembly. Openings in the soldermask selectively expose the underlying copper pads that need soldered connections. The width of these openings relative to the pad size is known as the opening shave.

This article provides a detailed overview of soldermask opening shave including its purpose, typical values, how it is designed, considerations for different pad shapes, and effects on manufacturability and soldering defects. Guidelines are provided for calculating appropriate opening shave widths based on pad geometries and solder flow needs.

Purpose of Opening Shave

The main objectives of providing additional open area around pads include:

• Exposes the surface of pad for sufficient solder wetting.
• Accommodates registration tolerances of soldermask alignment.
• Allows a channel for outflow of excess solder away from the pad.
• Improves manufacturability by reducing probability of mask openings shrinking smaller than pads.
• Lowers risks of solder bridging between neighboring pads.

Typical Opening Shave Values

Industry standard IPC-7351 specifies a minimum annular ring of 3 mils (75 μm) of open pad area extending beyond the soldermask on all sides. However, common design values are:

• Low density through-hole pads: 5 to 8 mils
• High density surface mount pads: 4 to 6 mils
• Fine pitch components: 3 to 4 mils

Higher opening shaves up to 10 mils may be used in vibration environments where soldermask separation risks are higher.

Design Factors for Opening Shave

Key considerations while designing opening shave include:

• Registration tolerance between pads and soldermask image
• Pad shape and orientation – square pads need larger shave
• Pad density – higher density needs tighter shave to avoid bridging
• Soldermask expansion space from pad for outflow
• Copper pad thickness – thicker copper allows slightly smaller shave
• Soldermask material – photoimageable masks hold registration better
• Vibration levels – shave increased at vibration prone regions
• Rework considerations – sufficient space for rework and solder cleanup

Opening Shave for Different Pad Shapes

Rectangular Pads

A symmetrical shave of 4-6 mils on all sides is typical. The long edge shave may be 1 mil higher if length exceeds 1.5 times width.

Square Pads

Require at least 4 mils additional opening on all four sides due to higher bridging risks along diagonals.

Rounded Pads

Here adjusted shave widths compensate for shorter distance along curved edges:

Rounded pad soldermask opening (Image Credit: PCB Square)

Effects of Inadequate Opening Shave

Insufficient shave exposing the pad can lead to:

• Dry solder joints or incomplete wetting if mask overlaps pad area
• Solder masking separation under thermal stresses, closing the designed openings
• Solder spread into narrow openings increasing bridging tendency
• Voids and trapped fluxes due to lack of outflow clearance
• Inability to clean undermask areas during rework

Solder Defects Related to Opening Shave

Various soldering defects can be caused or exacerbated by improper control of soldermask opening shave:

Solder Bridging

Pulling in of solder between adjacent pads when clearance space is inadequate.

Solder Balling

Fluid solder gathering into spheres instead of wetting pad surfaces when openings are mismatched.

PCB Delamination

Soldermask separation from pad edges under vibration or thermal stresses exposes more copper area.

Solder Beading

Ring-shaped solder bead formation along pad periphery when mask overlaps pad.

Solder Mask Slivers

Sliver-like leftovers of soldermask inside openings interfering with wetting.

Guidelines for Calculating Opening Shave

1. Determine pad size and shape

• Measure length, width for rectangular pads
• Define diameter for rounded pads

2. Account for soldermask registration tolerance

• Typically around 4 mils (100 μm)

3. Add minimum annular ring width

• IPC-7351 recommends 3 mils (75 μm)

4. Provide expansion clearance

• 2 mils for most pads
• 4 mils for large pads > 40 mil sides

5. Round shave dimensions up to nearest 0.5 or 1 mil grid

• Simplifies manufacturing tolerances

6. Increase shave for vibration exposure

• Add 2-4 mils for vibration prone regions

7. Verify shave against IPC or manufacturer’s guidelines

• Reshape pad if needed to allocate sufficient shave

Conclusion

The soldermask opening shave is a small but vital PCB design parameter that prevents defects and rework in assembly by properly exposing pads for clean soldering while limiting bridging risks. Applying appropriate shave margins based on pad sizes, shapes and density allows high soldering yield. As PCB fabrication precision improves, opening shaves continue to shrink permitting further miniaturization.

Frequently Asked Questions (FQA)

Q1: How is the registration tolerance between pads and soldermask openings reduced?

A1: Using photosensitive soldermasks exposed with the same PCB pad image minimizes image translation errors. Laser direct imaging can further improve alignment precision.

Q2: Which pad shape typically requires largest opening shave?

A2: Square pads need relatively larger shave margins along the pad diagonals to avoid bridging compared to rectangular pads. Rounded pads allow tightest shave due to reduced meniscus formation along curved edges.

Q3: How does soldermask thickness impact the opening shave?

A3: Thicker masks impart greater stress on pads risking delamination and separation. This may necessitate slightly higher shave values. Typical mask thickness is around 3-5 mils.

Q4: When is a larger than normal opening shave warranted?

A4: In vibration prone environments, where differential expansion might gradually expose more pad area. Also, where anticipation of numerous rework cycles requires extra clearance for cleaning undermasks.

Q5: How is opening shave optimized for fine pitch components?

A5: Reducing shave close to the minimum recommended values allows tighter packing while preventing bridging between adjoining pads. This requires high precision imaging and registration process capabilities.

How to design pcb soldermask opening

This article mainly introduces the opening of pcb. Firstly, it introduces opening and bright copper in PCB design. Secondly, it introduces how to realize the tinning of PCB wiring. Finally, it explains the steps of how to set the opeining.

What is the pcb soldermask opening?

The circuit on the PCB are covered with soldermask to prevent short circuits and damage the device. The so-called solder mask opening is to remove the paint layer on the circuit, so that the circuit can be exposed to tin.

As shown in the above picture, it is the opening. PCB opening is not uncommon. The most common one is probably the memory stick. The students who have removed the computer know that the memory stick has a gold finger, as shown below:

The golden finger here is to opeing, plug and play.

There is also a very common function of opening the opening, which is to increase the thickness of the copper foil in the later period, which is convenient for excessive current, which is more common in the power board and the motor control board.

opening and bright copper in PCB design

In the design, customers often ask for opening and bright copper. Because the customer is also ignorant or we are not too clear about this process, it is very troublesome to communicate. In our design, we often encounter customers who need to add shields, partial bright copper on the board side, through-hole open-resistance soldering, copper on the back side of the IC heat sink, and scratch pad. According to the actual situation, let’s take a look at several sets of pictures to explain.

1, shield

If the customer needs to add a shield, then all we have to do is add a Soldmask with a width of at least 1mm. If you need to add a stencil, you need to confirm with the customer. At the same time as adding the Soldmask, we need to spread the network copper in the add mask area, and we must cover the Soldmask plane, otherwise the pcb substrate (FR4, etc.) will be exposed. Other non-local networks should not pass through the Soldmask. Adding a loosemask area to the pcb effect reveals a yellow copper. Solder mask coverage is provided for areas that are not added.

2, solder mask opening hole

In the design, we often hear the whole plate plug hole or partial plug hole. When adding the hole, we pay attention to the fact that the plug hole company name generally refuels the BGA, and vice versa. ). In general, a company that has a specification of more than 12 mils must use a solder mask opening.

3, IC thermal pad

Generally, a solder-proof PAD is added on the back of the IC heat-dissipation pad (adding a shoulder mask larger than the surface layer or equal to the surface of the surface pad) and a ground hole, and a copper-clad solder mask is placed on the back surface to better pass the heat of the surface layer. The hole in the hole is transmitted to the back of the copper skin to disperse better.

4,The Pad tin touched

In wave soldering, in order to solve the problem of tin bonding caused by the tight pitch of the pads, we will use the shape of the scratch pad. Note that it is necessary to add copper bumps of the same size as the solder mask while adding the solder mask.

How to realize PCB trace opening

In the circuit vias, it is necessary to drive 8 relays. When the multi-channel relays are turned on, the current is greatly increased. To ensure the actual effect, while widening the current line, it is desirable to remove the solder mask on the current – the green oil layer, and the board is made. In the future, you can add tin to the top, thicken the line, and pass more current.

The actual results are as follows:

The implementation method is as follows:

Draw this line in the layer of the top PCB layer (or bottom layer depends on the layer where the preset line is located), and then draw the line that coincides with this in the top solder (or bottom solder) layer.

How to set the circuit to open

The PCB design can be used to set the opening on the TOP/BOTTOM SOLDER layer.

TOP/BOTTOM SOLDER (top/bottom solder mask green oil layer): The top/bottom layer is coated with solder resist green oil to prevent tin on the copper foil and keep it insulated.

A solder resist green soldermask opening can be placed on the pads, vias, and non-electric traces of this layer.

1. The pad will open by default in the PCB design (OVERRIDE: 0.1016mm), that is, the pad exposed copper foil, the outer expansion is 0.1016mm, and the wave soldering will be tinned. It is recommended not to make design changes to ensure solderability;

2, the via hole in the PCB design will open by default (OVERRIDE: 0.1016mm), that is, the through hole exposed copper foil, the external expansion 0.1016mm, the wave soldering will be tin. If it is designed to prevent tinning on the vias and do not expose copper, you must tick the PENTING option in the additional properties of the vias SOLDER MASK to close the vias.

3. In addition, this layer can also be used for non-electrical routing, and the green soldering resistance should be opened accordingly. If it is on the copper foil trace, it is used to enhance the overcurrent capability of the trace. When soldering, it can be tinned. If it is on the non-copper foil trace, it is generally designed for marking and special character silk screen, which can save production. Character silkscreen.