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What Circuits are Used to Generate Clock Signals?


Clock signals are essential timing references used to synchronize and coordinate the operation of digital logic circuits in integrated circuits and electronics systems. A clock waveform oscillates between a high and low logic level at a regular frequency. The transition edges trigger sequential logic state changes and digital computations. Clock signals must exhibit precise frequencies with low jitter and high spectral purity for reliable circuit operation.

Various clock generation circuits are available to produce different frequencies using crystal, relaxation, ring, and phase-locked loop oscillators along with frequency multipliers and dividers. Selecting the right approach depends on frequency stability, jitter, power and tuning range requirements. This article provides an overview of commonly used clock generation circuits highlighting their operating principles, characteristics, and applications.

Clock Signal Properties

Classic Circuit Analysis--Clock Circuit
Classic Circuit Analysis–Clock Circuit

Desirable attributes of stable clock signals are:

  • Accurate oscillation frequency matching system specifications
  • Low cycle-to-cycle jitter to precisely trigger logic
  • High spectral purity with minimal harmonics
  • Square waveform with fast rise and fall times
  • Constant peak-to-peak voltage amplitude
  • Low duty cycle distortion
  • High signal integrity over chip/board distribution

Crystal Oscillator

This uses the mechanical resonance of a vibrating crystal to generate a sinusoidal signal at a precise natural frequency determined by the crystal cut and dimensions. Feedback amplifiers sustain the oscillations applying bias voltages and limiting gain to overcome losses. Output buffers provide squared CMOS/TTL compatible clock outputs.


  • Excellent frequency stability and accuracy
  • Low jitter (<100 ps)
  • High spectral purity
  • Frequency range from kHz to MHz


  • Primary system reference clocks
  • Real-time clocks
  • RF systems
  • Instrumentation

Relaxation Oscillator

Here an RC network is repetitively charged and discharged between two voltage thresholds to produce a timing clock signal. Comparators switch the output state when the RC voltage crosses the thresholds.


  • No external components
  • Moderate accuracy and stability
  • Higher jitter
  • High power consumption


  • Embedded microcontroller clocks
  • Timer circuits
  • Low-frequency clock generation

Ring Oscillator

This consists of an odd number of inverting logic gates connected in a circular chain. The output of the last gate is fed back to the input of the first, causing oscillations at a frequency determined by the gate delays. Buffers provide synchronized outputs.


  • Completely on-chip integration
  • Tunable frequency by control voltage
  • Moderate jitter
  • Noisy output requiring filtering


  • On-chip clock generation
  • Analog-to-digital converters
  • Frequency synthesis in PLLs
  • Random number generation

Phase Locked Loop (PLL)

Classic Circuit Analysis--Clock Circuit
Classic Circuit Analysis–Clock Circuit

A PLL synchronizes its oscillator output to match either an external reference clock or crystal oscillator using a feedback control loop. The phase detector generates error voltages proportional to phase differences driving the oscillator frequency toward zero phase error.


  • Excellent frequency stability when locked
  • Very low jitter

-Tunable frequency multiplication/division

  • Integrated implementations


  • Microprocessor/communication IC clocks
  • Frequency synthesis of various clock rates
  • Clock recovery from data communications
  • Frequency modulation/demodulation

Clock Conditioning Circuits

Supplementary circuits help provide final clock signals with desired characteristics:

Frequency Multipliers

Use analog or digital techniques to generate harmonic multiples of an input reference frequency. Popular for sub-clock generation.


Divide input clock frequencies down digitally to lower clock rates using ripple counters or synchronous counters.


Provide periodic clock signal refreshment, fanning-out, and amplitude limiting to safely drive large clock distribution loads.


Remove noise and harmonics to improve spectral purity using LC and RC low-pass filters.

Clock Distribution

The generated clock is distributed to various logic blocks using balanced trees and grid networks overlaid on chip or board along with careful impedance control, termination and buffering to control reflections and skew.

Choosing Clock Generation Circuits

The table below summarizes the key selection criteria:

ParameterCrystal OscillatorRC OscillatorRing OscillatorPLL
Frequency StabilityExcellentPoorModerateExcellent (with reference)
Frequency TunabilityFixedLimitedExcellentExcellent
JitterVery lowHighModerateVery low
Spectral PurityExcellentModeratePoor (spurs)Excellent
Integration LevelExternalMediumHighHigh
Power ConsumptionLowHighMediumMedium


A wide variety of clock generation circuits provide multiple options to engineers designing digital systems, based on requirements like operating frequency, jitter tolerance, tunability, cost and power constraints. Proper selection coupled with robust distribution network design delivers stable synchronized timing signals vital for reliable functioning of synchronous logic circuits. Given their criticality, clocking circuits and techniques continue to be an area of innovation to support advancing chip technologies and faster computing systems.

Frequently Asked Questions (FQA)

Q1: Why is using a crystal oscillator better than an LC tank oscillator for clock generation?

A1: The precise resonant frequency of quartz crystals gives extremely stable and accurate clock signals in comparison to LC tank circuits which are susceptible to drift with temperature and component variations.

Q2: What techniques can be used to reduce clock jitter from oscillators?

A2: Using higher Q-factor crystals/LC tanks, providing sufficient loop gain in oscillator feedback paths, maintaining well-regulated bias voltages, filtering noise sources, and buffering clock signals before distribution help minimize jitter.

Q3: How does a phase-locked loop provide tunable clock generation?

A3: The voltage-controlled oscillator inside the PLL allows its output clock frequency to be tuned across a range determined by the VCO transfer characteristic. The PLL locks the VCO to an accurate reference input clock.

Q4: Why is clock signal integrity important in digital systems?

A4: Clean clocks with balanced rise/fall times, constant amplitude and shape are critical for synchronous digital logic. Noise, reflections, jitter degrade switching performance and computation reliability.

Q5: How can multiple clock frequencies be generated from a single reference source?

A5: Using a frequency divider produces integer sub-multiples of the source frequency. Frequency multipliers and mixers generate harmonic multiples. PLLs allow both integer scaling and arbitrary frequency synthesis.




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