Via In PCB Pad (VIP)


The rapidly increasing technological advancement in electronic products is demanding more compact, high performance, maximum functions and features in small package while available in less price and high quality and longer life time.

This wish list is the dream of every electronic product user and customer, while product manufacturers aim at less cost, high profitability and mass manufacturing. The core of all electronic products is PCB. So it is impossible to fulfill the wish list mentioned above without implementing those wish list on PCB as well.

Hence the multilayer PCB exponentially decrease the PCB size, while increasing layers and routing complexity also increasing the component assembly density. This enables manufacturing High Density Interconnect PCBs that having miniature SMT components like BGA, QFN packages assembled very closely tightly so as to be used in today’s advance electronic gadgets like smartphone, laptops, RAMs, wearable electronics, sensitive medical instruments like ECG and MRI machines and high tech military specification defense electronics products like GPS, navigation electronics, radar and aerospace industrial machines.

Via In Pad

What is Via in Pad..?

Among various techniques in designing the PCB layout for electronic device, the Via in Pad ( VIP) is also one of them. The VIP means placement of via beneath the component pad. This will save space on the PCB and hence can be used for routing. As we know that via is the interconnection between two traces of different layer either top to bottom or bottom to top or top to inner layer or inner layer to bottom. Via can carry the track from one point on PCB to other through switching between layers.

Via is the acronym of “Vertical Interconnect Access (Via)” can be blind via, buried via, through hole via and stacked via. The blind via is one that is connected from top or bottom layer to the inner layer. They can be seen from only one side of PCB. The buried via is connected between two inner layers and they cannot be seen from either side of PCB because they are hidden/buried inside the PCB. Through hole via connects the top and bottom and passes through all inner layers and can be seen from both sides of PCB.

What is Via in Pad..?

Via Stacking: On the other hand the stacked via is the vertical stacking up of two or more vias to make an interconnection between farther layers. Like if the interconnection is to be made between inner layer number 2 and inner layer number 4, the vias are “split” in two vertical vias i.e. one via will connect layer 2 to layer 3 and second via will connect layer 3 to layer 4 and the two vias are placed vertically upon each other to connect layer 2 and 4. This is called via splitting and stacking.

Micro-Via: For High Density Interconnect (HDI) PCB layouts, the miniature size vias are used called “Micro-via”. The diameter size of these micro-vias can be as low as 3 mil. Micro-vias holes are bored using high accuracy laser drilling. The micro-via can greatly increase the performance of HDI PCBs. The reliability of micro-via is very good. The diameter of micro-via is ultrasmall and trace length is also short. The micro-via can also reduce the inductance hence improving the signal integrity quality. It also reduces parasitic loading effect.


Micro-Via as VIP:

The micro-via can be via in pad and can be capped and filled with conductive (copper) or insulated (resin) filling. The via in pad that is placed on the pad of QFN package that is not under the body of component or not on the thermal pad, it must be filled with epoxy resin and covered / capped with copper plating. The resin filling is cost effective method (with respect to manufacturing) of capping via as compared to conductive copper filling. Many manufacturers avoid via in pad capping due to increases fabrication processing of capping and filling and hence more time and cost consuming.

It must be noted that, if the via in pad is not capped or filled, then the solder paste will flow/wick into the VIP during reflow process and can greatly deteriorate the solder joint. Hence via in pads must be filled and capped except thermal pads via in pads. For this purpose a separate drill file that highlights the vias that are in pads of components (that need to be filled and capped) must be sent to the PCB manufacturer / fabrication shop to avoid any mistake of capping and filling of traditional via.

Micro-Via as VIP


Via in Pad and BGA:

The fine pitch BGA packages are used in PCB layout where size is the important concern. Designers nowadays extensively placing via beneath the pad of BGA. In QFN and BGA packages specifically, the thermal pad found commonly in power ICs, via in pad plays important role. The VIPs placed upon the thermal pads are not capped nor filled with epoxy resin. This is done so as to provide enhanced thermal management in heat dissipation. The heat and gasses trapped during the reflow process due to solder paste flux can cause the BGA / QFN IC package / body to become tilted or lose flatness and will not remain coplanar. The VIP will allow heated gasses to have ventilation access to exit the IC package hence IC package surface remains smooth and coplanar. Also when the PCB manufacturing and PCBA is complete and PCB is working / operation under high temperature, the heat can easily be thermally conducted through these VIPs to the heat spreader and heat sinks. The VIPs under the thermal pads also allows the excess solder paste of thermal pad to drain through them hence further improving thermal management. For via in pad, the drill and the annular ring must fit inside the copper pad.

Via in Pad and BGA

Via in Pad and BGA

Advantages of Via in Pad (VIP):

Fine pitch BGA higher pin counts trace connections are routed efficiently due to ultrasmall size of micro-via VIP.

High Density Interconnect PCBs are not possible without VIP

Components placement require less board area

Increase the performance and reliability of board

Signal Integrity and quality is improved

Thermal management of PCB is improved by implementing VIP

VIPs are highly suitable for high speed circuit design

Reduce the inductance and parasitic capacitance and loading