Numerous printed circuit board layout & routing guidelines used presently aim to ensure signal integrity, even for speed signals & devices. For individuals new to printed circuit board design who have not encountered any signal integrity issues, the idea of guaranteeing signal quality in a layout may appear abstract. However, straightforward layout practices can help solve or prevent numerous problems that modern PCBs may encounter. The main objective of signal quality practices is to detect and rectify issues in a printed circuit board design. It ensures that digital/analog signals remain uncorrupted during transmission through interconnects and can be retrieved at the receiving end without degradation.
This guide aims to summarize signal integrity issues that may arise in the printed circuit board layout, along with fundamental remedies to address them. By incorporating these foundational techniques during the initial design stage, maintaining signal integrity throughout the routing process becomes more straightforward.
Fundamentals of Signal Integrity
At its core, the objective of applying signal integrity practices in printed circuit board layout & routing is to guarantee that the signal remains uncompromised as it travels from its source to its destination. In simple terms, the objective is to guarantee that the signal obtained at the ending point of the interconnect is a precise depiction of the signal initially transmitted at the beginning. Although a signal can never be completely free of distortion, following some fundamental practices can reduce signal distortion to a minimum and ensure that the receiving component always detects the accurate signal.
Implementing specific design practices can guarantee this outcome, starting from the schematic capture & film stack design phase. Proper stack-up design & finish assignment for ground, power, and routing can resolve numerous signal integrity, power integrity, and EMI/EMC issues. Additional uncomplicated methods consist of selecting the appropriate capacitor, computing impedance, and comprehending the constraints of single-conductor and differential traces.
When Should One Think About Signal Integrity?
Every design has signal integrity issues, but they typically do not impact a product’s functionality or generate excessive noise unless working with speedy digital signals/high-frequency designs. When dealing with these types of designs, there are several issues to consider.
- To avoid signal reflections, precise impedance calculations are crucial.
- Long can experience losses & dispersion during Fast switching signals can cause crosstalk.
- Extra radiation losses can manifest as significant noise in Electromagnetic compatibility tests.
- Regarding digital signals, issues like overshoot undershoot, and ground bounce can arise from excess inductance.
- Parasitics can lead to high-frequency signals becoming coupled and potentially degraded.
- Fiber weaves can cause skew and resonant frequency loss, negatively affecting signal timing and integrity.
- Jitter can occur in digital signals due to either random fluctuations or SI/PI/EMI issues.
- The copper surface texture along the distance of an interconnect can cause additional losses.
Signal integrity can be a challenging issue to tackle when dealing with high frequencies or fast switching speeds commonly found in speedy digital boards. Nonetheless, one should implement certain straightforward design measures to safeguard against these problems and prevent design failures.
Start Signal Integrity With Your Stackup
To ensure signal integrity, it’s essential to establish a well-defined ground & keep it near vital traces during the routing process. You can achieve it by implementing a well-planned stack up, carefully selecting ground & power planes, and appropriately assigning signal layers. By taking these steps, most electromagnetic interference (EMI) and signal quality issues can be effectively addressed. Additionally, a properly designed stack-up can have a positive impact on power quality as well.
The stack-up diagram below illustrates a common configuration that employs alternating layers of signal, power, and ground. In this case, the design incorporates ground layers near the analog layers to achieve shielding, establish a ground plane, and facilitate the definition of impedance lines (such as strip lines/microstrips). To prevent reflections, minimize radiation & reception of electromagnetic interference, and shield against signals on different layers, it is beneficial to establish a low-impedance return path with well-defined trace impedance and ground near signals.
The impact of layer thickness on losses in digital/analog signals transmitted through stripe lines, microstrips, and coplanar arrangements is a widely recognized phenomenon. One way to mitigate losses is by carefully selecting the dielectric thickness for signal coatings that carry high-speed or high-frequency signals. By selecting appropriate materials & plating for traces, it is possible to achieve reduced losses at very high frequencies, particularly in mmWave layouts that demand accurate signal integrity. Implementing these measures collectively can guarantee minimal signal losses during transmission through an interconnect to its final destination.
Significance of Impedance & Routing for Signal Integrity
After finalizing the stack up and placing crucial components, the layout process entails tracing the routes. Impedance requirements, as specified by signaling standards employed in user interfaces & high-frequency signals, must be adhered to to ensure the quality of signals & prevent complications in speedy channels. While routing, particular attention must be given to key geometric characteristics of tracks on the printed circuit boards.
- To achieve optimal impedance, single-ended & differential signals must be considered.
- Differential pairs require consistent spacing & length-matching tolerances to ensure proper impedance.
- Maintaining a tight path throughout the signal route is crucial and can be achieved by using uniform planes & grounded vias.
- Decreasing via transitions & excessive bends is important, especially at frequencies of 10 GHz and above.
- Via stubs should be removed from the fastest and highest frequency signal routes.
The initial two points aim to guarantee that the capacitance along a pathway adheres to the prescribed design value outlined in the applicable signaling protocol. The 3rd point pertains to minimizing EMI & noise interference by ensuring that the signal current formulated by high-speed or high-speed signals has minimal inductance. The last two points focus on eliminating loss & echo at any point of impedance variation along a pathway.
Components such as vias and connectors may have an input capacitance that diverges from the desired value. Design rules are implemented to ensure these specifications are met during the design process.
Your printed circuit board design software’s routing tools can convert your routing specifications into layout rules to ensure that you meet your goals for impedance via count, spacing & return path. Backdrilling incurs a price tradeoff that affects signal integrity; therefore, it should be applied only to fast digital signals and as a last resort if there are no other routing options available to reduce the requirement of back drilling.
Together, these steps can effectively tackle issues that may result from reflections, including intersymbol interference within an eye pattern and standing waves on transmission lines that are not properly matched.
Identifying Problems of Signal Integrity
Detection of signal integrity issues requires either simulations/measurements. It is preferable to perform simulations during the design phase to detect and address potential signal integrity issues before prototyping. An effective approach is to make test circuit boards for the layout, enabling measurements to be taken before moving into high-volume production. Regardless of the chosen approach, identifying signal quality issues should be finished before scaling the layout for high-volume creation.
Simulations During Routing
In the layout phase, certain ECAD packages can detect signal integrity issues through simple simulations. Crosstalk waveform calculations & ringing are two common emulations that could be simultaneously executed. The information can typically be specified in datasheets. By running these simulations, one can understand the impact of terminations & interconnect spacing on the transient response of the interconnects.
There are additional points to verify while routing, such as:
- Undershoot and Overshoot
- Fall time or Rise time during switching
- Skew present in both differential pairs and parallel buses
- ground continuity
You can use advanced ECAD software packages with online simulation tools to verify these points during the PCB design process. After routing the design, an electronic design automation (EDA) tool can assess these points. It ensures that the signals on every interconnect stay within sound margins. It also exhibits the necessary response as perceived at the receptor component.
Detecting these issues in the initial stages of the layout process can help resolve numerous signal quality problems, potentially eliminating the need for complicated & time-taking redesigns.
Possible Problems Due to Weak Signal Integrity
The impact of obstruction on the functioning of electric appliances can be quite significant. In the past, flight attendants would advise passengers to turn off their cell phones. We would encounter radios that created static audio. Additionally, certain older computers emitted so much Electromagnetic interference that they were removed from the market. Signal integrity issues typically manifest in more subtle ways than obvious performance degradation. Examples include intermittent data loss, occasional glitches, or even complete device failure in extreme situations. These problems are often rooted in signal integrity issues.
With the rise in signal speeds of modern electronics, they become increasingly vulnerable to aggressive interferences, such as impedance mismatch-induced signal reflections, ground bounce & crosstalk.
Without appropriate countermeasures in the printed circuit board layout, these issues can cause signal degradation. Then, it ultimately renders the system inoperable. Apart from avoiding signal integrity issues in external components, it is equally important to ensure that the printed circuit board does not contribute to signal quality issues for its circuit or other electronics. Therefore, before delving into the specifics of designing for such problems, it is essential to have a solid grasp of the critical signal quality fundamentals.
Be Aware Of The Fundamental Signal Integrity
Various factors can contribute to signal degradation on a printed circuit board, which can be classified. Below are four key areas of inadequate signal quality that require attention.
· Electromagnetic Interference (EMI)
Improper routing of high-speed signals on a circuit board can result in the emission of electromagnetic interference (EMI). It’s not just the length and arrangement of the traces that can cause issues, but also the trace & via stubs that act as the antenna and contribute to the problem. EMI can also arise from the signal path. It should ideally be on the adjacent ground plane to minimize its effects. Any obstruction in the ground path can cause the signal to emit even more sound as it tries to find its way back to the source.
· Unintentional Electromagnetic Coupling (Crosstalk)
When high-frequency traces are placed too close, they can unintentionally interfere, causing one signal to overpower another. This interference, known as crosstalk, can cause the affected signal to imitate the properties of the disruptive signal and fail to carry out its intended function. Crosstalk is not only a concern for footprints that are located adjacent to the same layer. But also for traces that run parallel to each other on side-by-side layers of a circuit board, this form of crosstalk is transverse coupling. That’s why many circuit board layouts adopt alternating vertical and horizontal directions on side-by-side layers to mitigate this issue.
· Simultaneous Switching Noise (Ground Bounce)
On a printed circuit board, when numerous components switch between low and high states. The current level may not return entirely to the ground potential during the falling edge if the voltage level during the falling edge transition rises excessively. The low-level signal is identifiable as the high-level. When this phenomenon happens concurrently, it can result in double or false switching, leading to circuit operation disruptions.
· Impedance Mismatch
When the consistency of high-frequency transmission lines is alterable, it may cause signal echo that compromises its integrity. Traces routed without proper consideration for their capacitance value are prone to changes in value in different areas of the board under varying conditions. To ensure the appropriate routing of impedance-controlled traces, a trace width, certain layer configuration & clearance are necessary.
Now that we have identified the primary signal integrity issues, let’s examine some printed circuit board design procedures that can mitigate these problems.
PCB Layer Configurations and Component Placement
Signal integrity issues in PCBs commonly arise from inadequate signal ground paths. To ensure optimal signal integrity, the ground path must be unobstructed and located on a close reference layer. To make it work, you need to arrange the layers in the board in a specific way that separates the sensitive high-speed routes and keeps them close to reference planes. This arrangement can be either in a microstrip or stripline style. In a microstrip setup, the traces are located on the surface and have only one underlying plane. In contrast, in a stripline setup, the traces are available internally and are sandwiched between 2 reference planes.
It’s good to have a reference plane next to signals so they can travel back smoothly. However, it becomes even more critical for delicate signals that require controlled impedance routing.
To figure out how wide a path should be for this kind of routing, you have to calculate the width & strength of the material around it, as well as the thickness of the path itself. Before starting the layout process, designers need to decide how they want the circuit to look because changing the board layers or substances used for making the PCB can affect their plans.
After determining the circuit stack-up layer configuration, the next stage involves placing the elements on the circuit. High-frequency circuits often contain multiple nets that originate from the source of one component, traverse via other parts, and terminate at a load sensor of the last component. You should maintain the signal paths in a circuit to preserve their signal quality.
It requires placing the components in sequence as indicated in the blueprint, allowing for the short link between pins. Space the other elements, like processors & memory chips. It helps to accommodate their routing techniques while also being close to short links. Here are the additional essential considerations to remember during component placement.
· To ensure proper placement of high-frequency circuitry, it’s important to follow these guidelines:
- Situate bypass capacitors near the power connectors of processor & memory applications.
- Allocate sufficient space for both bus routing & escape routing.
- Also, Follow the assembler’s layout for DFM guidelines.
- Guarantee that hot-running elements are properly cool down
With the parts on the board, the next step is routing.
Signal Integrity Trace Routing and Planes
Once you reach this stage, you’ll commence trace routing. However, it’s important to remember that the quality of signal integrity is highly dependent on the placement of the components. For instance, you should meticulously plan the escape routing to guarantee that all the signals are accompanying components. Many designs rely on via-in-pad for large pin-count BGAs to keep connections short and open up more room for routing.
When you position the components optimally, you can route high-frequency circuitry effectively. Nevertheless, there are some guidelines to bear in mind before you proceed:
- Ensure that signal traces are direct and short.
- Whenever feasible, route sensitive signals on inner layers & alongside or between standard planes.
- It is important to keep clock lines & other high-frequency signals isolated from other places. A useful guideline to follow is to maintain a spacing that is three times the width of the trace being useful.
- Ensure that differential pairs are together and avoid separating the couple around obstructions.
- If you connect a bunch of wires that need to be the same length, begin with the long and then make the other wires go the same length by adding curves where needed.
- Don’t put important wires through places on the circuit board where there is a lot of electrical noise, like where the power goes or the analog signals are.
- If necessary, provide enough space for certain routing topologies like daisy chains.
- To prevent additional signal integrity issues, limit using through-holes and minimize their inductance and length.
Apart from routing, it is essential to make the power PDN for the board. A clear PDN is essential for maintaining power integrity and promoting good signal quality. Moreover, it’s crucial to avoid routing high-frequency transmission lines via blocked areas on a standard plane.
Routing high-speed transmission lines through blocked areas on the reference plane can result in increased electromagnetic interference (EMI) generated by the board.
How to improve signal integrity?
· Stackup definition
To ensure good impedance control, it is important to balance size, cost & signal integrity when choosing the number, type, and arrangement of the PCB layers. A general guideline is to incorporate power & ground planes. To ensure optimal signal path continuity, we recommend distributing the planes in the stack up evenly. Ideally, at least one plane should be adjacent to each signal layer without any breakpoints. Additionally, one can carefully evaluate the material properties, such as copper thickness, dielectric thickness, and dielectric constant, as they play a significant role in signal performance.
When it comes to circuits with fast signal transmission, traditional materials like FR-4 may not be the optimal choice. Instead, we recommend opting for laminates with less Dk, as they can minimize distortions & phase variations in the signal. Rogers laminates, like Rogers RO4350, are excellent examples of such materials. Although they may come with a higher price tag, they offer certain properties tailored to high frequencies surpassing FR-4.
· Impedance control
Impedance control involves determining the optimal relationship between the positioning and size of PCB traces and the characteristics of the foundation to ensure that the signal intensity remains within predefined boundaries. Effective coupling achieves a strong signal, while poor coupling results in power losses & compromises signal integrity.
To achieve effective impedance coupling, the PCB traces need to have consistent geometry, which ensures a uniform Dk along the whole trace. To verify the impedance (capacitance) value, designers can adjust the width of tracks & utilize specialized calculators that are readily accessible online. Neglecting this aspect can lead to signal reflections, where the signal reflects its origin point. It reduces signal strength reaching its destination, and there is an increased risk of EMI. It results in reducing signal strength reaching its destination.
Signal Integrity in PCB Manufacturing
The integrity of a signal is closely related to the routing of high-frequency transmission lines, and effective routing techniques begin with the careful placement of components. Initially, identify the functional areas of the board,. One can place components in a way that offers the shortest & direct signal tracks for high-frequency circuits. However, before commencing with component placement, it is essential to create a board stack-up that will optimize the impedance traces for the layout.