When the digital circuit outputs a high level, the current drawn from the power supply Ioh and the current Iol injected at the low level output are generally different, that is, Iol>Ioh. The TTL NAND gate in the following figure illustrates the formation of a spike current:
The output voltage is shown in the figure (a) on the right. In theory, the waveform of the power supply current is shown in the right figure (b), and the actual power supply current is as shown in the right figure (c). It can be seen from Figure (c) that the supply current has a short and large amplitude spike when the output transitions from low to high. The waveform of the peak supply current varies with the type of device used and the capacitive load connected to the output.
The main reasons for the spike current are:
The T3 and T4 tubes of the output stage are simultaneously turned on in the short design. During the NAND gate output low level to high level, the negative transition of the input voltage produces a large reverse drive current in the base loop of T2 and T3, because the saturation depth of T3 is designed to be better than T2. Large, reverse drive current will cause T2 to first de-saturation and turn off. After T2 is turned off, its collector potential rises, turning T4 on. However, at this time, T3 is not out of saturation, so in a very short design, T3 and T4 will be turned on at the same time, resulting in a large ic4, causing the supply current to form a peak current. R4 in the figure is designed to limit this spike current.
The R4 in the low-power TTL gate is large, so its peak current is small. When the input voltage changes from low level to high level, the NAND gate output level changes from high to low, and T3 and T4 may also be turned on at the same time. However, when T3 starts to conduct, T4 is in an amplified state, and the collector-to-injection voltage of the two tubes is large, so the peak current generated is small, and the influence on the power supply current is relatively small.
Another cause of spike currents is the effect of load capacitance. The NAND gate output actually has a load capacitance CL. When the output of the gate transitions from low to high, the supply voltage is charged to the capacitor CL by T4, thus forming a spike current.
When the output of the NAND gate transitions from a high level to a low level, the capacitor CL is discharged through T3. At this time, the discharge current does not pass through the power source, so the discharge current of CL has no effect on the power supply current.
