Quick Presets

Layer Assignment (12 Signal + 6 GND + 6 PWR)
L1 SIG
L2 GND
L3 SIG
L4 PWR
L5 SIG
L6 GND
L7 SIG
L8 PWR
L9 SIG
L10 GND
L11 SIG
L12 PWR
L13 GND
L14 SIG
L15 PWR
L16 SIG
L17 GND
L18 SIG
L19 PWR
L20 SIG
L21 GND
L22 SIG
L23 PWR
L24 SIG

Copper Layers (24)

Prepreg Layers (12)

Core Layers (11)

Total Board Thickness
4.000mm
4000 µm
vs 4.0mm
+0 µm
Copper (24L)
840 µm
Prepreg (12L)
1482 µm
Core (11L)
2000 µm
12
Signal
6
GND
6
PWR
10
Stripline

Stackup Visualization

Outer SIG
Inner SIG
GND
PWR
Prepreg
Core
💡 24L Targets
3.5mm: High-density HDI
4.0mm: Standard 24L
4.5-5.0mm: Server/HPC
5.5-6.0mm: Backplane
📐 Impedance
Microstrip: L1→L2, L24→L23
Stripline: All inner SIG
Center: L12↔L13 PWR/GND pair
⚡ Power Integrity
6 GND: Every 4 layers
6 PWR: Multi-rail splits
L12-L13: Ultra-low Z pair
🔌 Applications
AI/ML: GPU/TPU modules
Network: 800G switches
HPC: Supercompute nodes
🔧 24-Layer Design Strategy
12 Signal Layers: L1, L3, L5, L7, L9, L11, L14, L16, L18, L20, L22, L24 — Maximum routing density for ultra-fine-pitch BGA (0.25mm), HBM3/HBM3E, 224G PAM4 SerDes, PCIe Gen6, CXL 3.0, and UCIe interfaces.
6 GND Planes: L2, L6, L10, L13, L17, L21 — Ground reference within 3-4 layers of every signal; symmetric distribution minimizes return path inductance and EMI.
6 PWR Planes: L4, L8, L12, L15, L19, L23 — Support 8+ voltage rails with island splits; L12-L13 form ultra-low-inductance decoupling capacitor structure.
Sequential Lamination: Requires 3+ lamination cycles with blind/buried vias, stacked/staggered microvias, and potentially ELIC (Every Layer Interconnect).
Materials: Ultra-low-loss required (Megtron 7, Tachyon 100G, I-Speed, EM-890K) for 56Gbps+ channels. Dk ~3.0-3.3, Df <0.002.
Symmetry: Structure symmetric about L12-L13 center for optimal CTE matching, <0.4% warpage, and reliable assembly of large BGAs/LGAs.