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What Is Xilinx XC7Z020-2CLG400i ?

The Xilinx XC7Z020-2CLG400i device belongs to the Zynq-7000 family and is grounded on the SoC architecture of Xilinx. The device is integrating a dual or single-core ARM Cortex processor that has rich features. The processor is grounded on the processing system and is having 28nm of programming logic. The central processing unit of the device is considered the heart of the processing system and is comprising of on-chip memory, state-of-the-art interfaces for peripheral connectivity, and interfaces for external memory too. The central processing unit has 2.5 DMIPS per MHz through each CPU with a frequency capability of 1 GHz. The device has coherent multiprocessor support, a couple of triple-timer counters, a global timer, 3 watchdog timers, and interrupts.

The device has caches of up to 32Kb of level-1 that have 4-way set-associative instructions and is independent of each CPU. There is also a 512Kb of level-2 that has 8-way set-associative instructions and is shared in between central processing units. Furthermore, the caches are having byte-parity support as well. Xilinx XC7Z020-2CLG400i has 256Kb On-Chip RAM and ROM with byte-parity support. This IC has a multi-protocol controller for dynamic memory with 32 or 16-bit interfaces for LPDDR2, DDR2, DDR3L, and DDR3 memories. The device has 16-bit support for ECC. It has an SRAM data bus of 8 bits with 64Mb support, parallels support for NOR flash, and 8 channel DMA controller capable of support for scatter-gather transactions, peripheral to memory, memory to peripheral, and memory to memory. The interconnects of the device are having a high-bandwidth connection for its PS and among PL and PS. The configurable logic block of Xilinx XC7Z020-2CLG400i has cascaded adders, flip-flops, and lookup tables. Block RAM is dual-port, expandable up to 72 bits, and can be configured in the form of dual 18Kb block RAM too. The DSP block has a pre-adder of 25-bit, accumulator or adder of 48-bit, and a signed multiplier of 18×25 bits. Its PCI block is supporting up to 8 lanes, 2nd generation speeds, along with endpoint configurations, and root complex.

Family Description of Xilinx XC7Z020-2CLG400i


The family of Xilinx XC7Z020-2CLG400i is Zynq-7000 which offers scalability and flexibility of FPGAs delivering ease of use, power, and performance usually associated with ASSPs and ASICs. The devices of this family are allowing the designers to target cost-sensitive and higher performance enabled applications through a single platform through the use of tools of industry-standard. All of the devices of the family are having identical PS but PL and input/output resources are varying in all devices. The device is utilized for a wide range of applications as in the automotive industry it has applications in driver assistance, information for drivers, and infotainment. It is used in broadcast cameras, machine vision, industrial networking, and motor control. Smart and IP cameras have also been used along with baseband and LTE radios. The device is used in biomedical imaging, diagnostics, multi-function printers, night-vision equipment, and video devices.

Memory Interfaces

The unit of memory interfaces of the Xilinx XC7Z020-2CLG400i device is comprising of controllers for dynamic and static memory interfaces. The interface for dynamic memory is supporting DDR3L, LPDDR2, DDR3, and DDR2 memories. While the interface of static memory is having support for interfaces of NOR flash, quad-SPI flash, parallel data bus, and static flash interface.

Interfaces for Dynamic Memory

The DDR memory controller which is a multi-protocol controller could be configured for delivering 32 or 16-bit broad accesses to its 1Gb address spaces through the utilization of a unity rank configuration for 8, 16, or 32-bit DRAM memories. The support for ECC is in the form of a 16-bit mode for bus access. The PS of Xilinx XC7Z020-2CLG400i is incorporating both associated PHY and DDR controllers encompassing its integrated inputs/outputs. The device is supporting up to the speed of 1333Mb/s for its DDR3 support. The DDR memory controller is multi-ported and is enabling the system processing and its programmable logic for common access to have a shared memory. There are 4 AXI slave ports in the DDR controller for this purpose. One of the 64-bit ports is having the purpose of ARM CPU through the controller of L2 cache and could be configured for lower latency. Two 64-bit ports are dedicatedly assigned to PL access. One of the 64-bit AXI ports is common for all of the AXI masters through a central interconnect.

Interfaces for Static Memory

The memory interfaces of Xilinx XC7Z020-2CLG400i for static memory are supporting external static memories. The 8-bit SRAM data bus is supporting till 64Mb, while the 8-bit NOR flash parallel data bus supports up to 64Mb. The integrated ONFI NAND flash is supporting up to 1-bit ECC. Whereas, 1, 2, and 4-bit SPI or a couple of quad-SPIs each of 8 bits are supported through serial NOR flash.

The Input / Output Peripherals of Xilinx XC7Z020-2CLG400i

The input/output peripheral unit of the device is consisting of peripherals for data communication. The key features of the unit comprise two tri-mode peripherals for Ethernet MAC having support for IEEE standard 1588 and IEEE standard 802.3. The device also has the capability of scatter-gather DMA. Xilinx XC7Z020-2CLG400i has a feature for recognition of 1588 revision for 2 PTP frames. It also supports an external PHY interface along a couple of USB 2.0 peripherals of OTG mode each having support of 12 endpoints. The device is entirely compliant with USB 2.0 standards with host and device IP core. It delivers an 8-bit external PHY interface for ULPI. It has 2 full CAN buses fully compliant to CAN 2.0B interfaces. With the utilization of its TrustZone system, 2 ethernets, 2 SDIO, and 2 USB ports are configurable in both non-secure and secure modes. The input/output peripherals are also communicating with the external devices via shared pool of 54 integrated multi-use input/output pins. Every peripheral could be assigned to either of its many pre-defined pin groups that enable flexible assignment of numerous devices on a simultaneous basis. Though all of its 54 pins are not capable to be used simultaneously for its input/output peripherals but most of its input/output interfaces for signals are available for PL to enable utilization of standard PL at input/output pins in powered ON conditions.




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