Skip to content

What Is Xilinx Spartan FPGA?

Most ultra-modern electronic applications need extraordinary capacity, bandwidths, and high-performance processor technology. In most instances, such electronics need a small FPGA footprint as well. Xilinx Spartan FPGA is one such processor component that will always cover these bases, making it ideal for consideration when designing and developing high-end computing electronic products. Xilinx spartan FPGA is a type of programmable logic device that is used for designing embedded systems and electronics.

But what exactly does it all entail? How is it beneficial to the electronic design process? This article will cover every important detail about the Spartan FPGA series from Xilinx. So hold on, and let’s dive right into it.

What is Xilinx Spartan FPGA?

Spartan FPGAS is a flagship product series from Xilinx. It offers system integration and system performance optimization. While Xilinx provides a wide multi-node portfolio that addresses needs across diverse applications, Spartan FPGA represents a key product-line solution.

FPGAs represent crucial semiconductor devices that depend on the CLBs (configurable logic block) matrix and get connected through programmable interconnects. It is also possible to reprogram FPGAs to a desired functionality or application requirement post-manufacturing. Such an attribute distinguishes it from ASICs that prove specific for the designed task.    

Xilinx Spartan FPGA series comes as a cost-optimized portfolio. It has diverse families, including the original Spartan, Spartan II, Spartan-3, Spartan-6, and Spartan-7. The original Spartan came to the fore in 1998. However, with time, Xilinx has advanced newer generations of Spartan devices. Each new generation provides adaptable technology and solution to address the needs of the industry.

Some integral and historical tech enhancements include major increases in performance, logic density, local memory, and I/O bandwidth. For instance, the original Spartan had a maximum of 1862 LCs (logic cells). Currently, new generations such as Spartan-7 FPGAs possess over 215000 LCs. Another key comparison includes the clock speeds that morphed from the original 80MHz on the initial Spartan to today’s 600MHz Spartan devices. The same has happened with the local memory and I/O bandwidths. What’s more? New Spartan FPGA generations have high-performance and cutting-edge capabilities such as mixed-signal capability, digital signal processing, and security.

Spartan FPGAs are vital computing components for numerous day-to-day electronic products. It spans from enhancing auto safety, helping with kid entertainment, handling huge LED signage, and enabling medical technologies to enhance medicine. Therefore, if you want help with some of these products, who better to contact than RayMing PCB and Assembly? You will get expert guidance, fabrication, and assembly services.

Important Xilinx Spartan FPGA Families

Xilinx Spartan-6 FPGA Family

Xilinx Spartan 6 FPGA

The FPGA family offers excellent system integration capabilities but with the lowest overall cost for high-volume applications. It has thirteen constituent members and delivers an expanded density that ranges from 3840-147443 LCs. The family’s power consumption proves half of that of prior Spartan families. It is also faster and with more ample connectivity.

Xilinx Spartan-6 utilizes the mature 45nm low-power copper process technology. The tech ensures an optimal balance when it comes to performance, cost, and power. It, therefore, provides a fresh, extra-efficient, dual-register 6-input LUT logic besides a rich assortment of built-in and system-level blocks. It includes 18kb block RAMs, among other valuable features. Such features offer a low-cost programmable option to traditional ASIC products, complete with unparalleled ease of use.

Spartan-6 provides an excellent solution for cost-sensitive embedded applications, high-volume logic, and consumer-oriented DSP designs. It is the programmable silicon base for targeted design platforms (TDP). Such, in turn, provides integrated or unified software and hardware components that help designers focus on innovation once their development cycle starts.

One tool commonly used and one you must familiarize yourself with is the Vivado. It becomes useful when trying to design a Spartan-6 Vivado. The program accommodates Spartan-7 and other series but hardly Spartan-6. Therefore, changing the description to Spartan-7 becomes crucial to ensure the realization of any success. Additionally, understanding the attributes of the Spartan-6 FPGA becomes crucial before embarking on the design and fabrication process.       

Attributes:

Configuration

Xilinx Spartan-6 stores the personalized configuration data in the internal latches of SRAM-type. Configuration bits amount from 3-33 Mb basing on the size of the device and the implementation alternatives when it comes to user design. It (configuration storage) is always volatile and thus the need for reloading whenever the FPGA becomes powered up. Further, the storage can also get reloaded at any given time, as long as you trigger a low on the PROGRAM_B pin through a pull. Data formats and loading configuration methods come in diverse types.

The bit-serial configuration comes either as slave serial or master serial mode. Master serial encompasses a situation where the FPGA forms CCLK signal, whereas the slave mode is when external configuration data source clocks the FPGA. Master SelectMap mode creates the CCLK signal for byte-wide configuration. It then gets received by the slave SelectMap mode, especially for the 8-bit and 16-bit-wide transfers. The JTAG pins available deploy boundary-scan protocols when it comes to the loading of bit-serial configuration data.  

Information on the bitstream configuration gets generated by the BitGen program. Two popular and typical configuration methods entail the SPI and the BPI. However, the Spartan-6 FPGA self-configures from an attached SPI flash PROM. It also supports MultiBoot configuration and includes a distinct factory-programmed device DNA identifier, essential for tracking purposes.   

CLBs, LUTs, and Slices

Every CLB or configurable logic block in a Xilinx Spartan-6 FPGA board comprises two slices arranged side-by-side. The architecture of the PGA possesses three CLB types in SLICEL, SLICEM, and SLICEX. Every slice has four LUTs, a miscellaneous logic, and eight flip-flops. LUTs prove essential in sequential and general-purpose combinatorial logic support. Therefore, synthesis tools often take advantage of these efficient arithmetic, logic, and memory attributes.

  • SLICEM. It forms a quarter of the FPGA slices in Spartan-6, with each of the four LUTs can get configured as a 6-input LUT containing a single output. The alternative is dual 5-input LUTs possessing identical 5-bit addresses and two independent outputs.
  • SLICEX. Comprises of 50% of all slices and have a similar structure to that of SLICELs save for the wide multiplexers and arithmetic carry option.
  • SLICEL. Comprise of 25% of the overall Spartan-6 slices. It contains SLICEM attributes save for shift/memory register function.

Clock Management

Every Spartan-6 FPGA possesses up to six CMTs. The CMTs have two DCMs each and a PLL that can get deployed individually or in a cascaded fashion. It is, however, prudent to understand the role of some of the clock management aspects.

  • DCM. It offers four phases of the CLKIN input frequency (shifted 270°, 180°, 90°, and 0°). Additionally, it delivers a double-frequency CLK2X complete with its complement in CLK2180.
  • Frequency synthesis. It comes independent of the standard DCM as CLKFX180 and CLKFX. Both can get programmed to provide any output frequencies.
  • Phase-shifting. It is possible to shift all the nine CLK outputs by a standard amount.   
  • Spread-spectrum clocking. The DCM is capable of accepting and tracking standard spread-spectrum clock inputs. It carries out this provided the input clock specs abide by the listed one in the datasheet.  
  • PLL. It serves the function of synthesizing a diverse range of frequencies besides filtering jitter for incoming clocks. It has the VCO (voltage-controlled oscillator) as its heart and a range of frequencies from 400MHz-1080MHz. The PLL has three programmable frequency divider sets to help adapt the VCO into the desired application.
  • Clock distribution. Every Spartan-6 FPGA offers a lot of clock lines to address diverse clocking needs of high fan-out, short propagation delay besides a low skew. The FPGA contains I/O clocks and 16 global clock lines.

Block RAM

All Spartan-6 FPGAs possess between 12 and 268 dual-port RAMs. Every RAM stores 18kb, with each having two autonomous ports that only share the stored data. Block RAM can either have asynchronous operations or one with programmable data width.  The synchronous operation features memory access (whether it entails “write” or “read”) getting controlled by the clock.

Input/Output (I/O)

The I/O range of pin numbers from 102-576 depends on a device and package size. I/O pins are configurable and comply with numerous standards. Aside from the few dedicated and supply pins, all other pins tend to have related I/O abilities. However, these only become constrained by particular banking rules. It is true, though, that all user input/output is bidirectional.

The I/O pins come structured in banks. Smaller devices have four banks, while larger devices contain six banks. Every bank possesses numerous typical VCCO output supply-voltage pins that also power certain input buffers. Plenty of I/O attributes are always at the designer’s disposal. Therefore, a designer can invoke such features based on their design.     

Low-Power Gigabit Transceiver

It is a certainty that each Spartan-6 development board you come across will possess a 2-8 gigabit transceiver circuit. Every GTP transceiver is composed of a combination of a receiver and a transmitter. It is capable of functioning up to 3.2 GB/s data rates. The receiver and the transmitter are different circuits and use separate PLLs to multiply the reference frequency input with specific programmable numbers ranging from 2 to 25.

Xilinx Spartan-7 FPGA

Xilinx Spartan-7 FPGA

Spartan-7 is the most recent addition within the cost-optimized portfolio from Xilinx. It provides the best performance (for every watt) and small factor packaging in meeting stringent requirements. The Spartan-7 FPGA devices have a MicroBlaze soft processor that runs over 200 DMIPs with 800Mb/s DDR3 support entrenched on the 28nm technology. Further, devices within this product line provide integrated ADC, Q-grade, and dedicated security characteristics on every commercial device. Such devices prove ideal for consumer, automotive, and industrial applications. It can also include any-to-any connectivity, embedded vision, and sensor fusion.

Attributes

28nm TSMC HPL Process Technology

The Spartan-7 FPGA contains the 28nm TSMC HPLC tech that ensures delivery of the best-in-class performance-per-wat. It is scalable with a CLB architecture complete with flexible LUTs. The LUT is configurable as distributed RAM, shift registers, or logic. Logic cells range from six thousand to a hundred and two thousand for system-level integration.

Embedded Processing

The Spartan 7 development board contains the MicroBlaze soft processor that gives it faster-embedded processing.  It has over 200 DMIPs MicroBlaze processors within the microcontroller. It also contains a real-time processor or an application processor configuration to choose from.

Low-Cost Design

The Spartan-7 FPGA series comes with a cost-optimized architecture. The multiple and efficient integrated blocks for BOM reduce costs. It includes XADC dual 12-bit ADCs (analog-to-digital converters) with thermal monitoring and supply voltage. Optimized selection of input/output standards also features predominantly.  

IMBC or Integrated Memory Block Capacity

The block RAM comes with incredible flexibility and with up to 4.2Mb. It is a high-performance and efficient block RAM capable of the byte write and an optional FIFO configuration. With a total of 36000 blocks, it can get split into two autonomous 18000 blocks.

Soft Memory Controller

The Spartan-7 FPGA line comes with an effective soft memory controller that guarantees ultimate flexibility. It supports DDR3/DDR2/LPDDR2, with data rates of up to 800Mb/s. Besides these, the product line has superior pinout flexibility with a software wizard to offer guidance throughout the process.

SelectIO Interface Technology

The Spartan-7 FPGA series has a multi-voltage and a multi-standard SelectIO interface. It banks an aggregate bandwidth of 240 GB/s with data rates of up to 1.25 GB/s LVDS. It also has 3.3V to 1.2V input/output protocols and standards. What’s more? It has adjustable slew rates to enhance signal integrity besides SSTL and HSTL memory interfaces.    

Effective DSP48E1 Slices

The DSP48E1 slices ensure high-performance arithmetic besides signal processing. Every slice possesses a quick 18×25 wide multiplier that has a 25-bit pre-add and a 48-bit accumulator. Because of these slices, it is adept up to 176GMACs at 551MHz. Further, pipelining, cascading, balancing, integrated pattern detect, SIMD support, and ALU.

Broad Design Security

Spartan-7 FPGA possesses comprehensive design security that reduces system cost, escalates reliability, and protects your design. It also has identifies such as the device DNA serial number and the eFUSE. Further, it also has the SHA-256 authentication and AES256 decryption for bitstream. Another design security feature comes in the form of tamper response and monitoring.

A Small, Packaging that is RoHS 6/6 Compliant

The product line is cost-optimized and flexible for challenging mechanical applications because of its small packaging. It comes with a package footprint of 8mm–27mm at a pitch of 0.5mm–1mm. It also possesses an extensive footprint-compatible package migration.

Xilinx Spartan-3e FPGA

Xilinx Spartan-3e FPGA family specifically aims to meet the requirements of cost-sensitive, high-volume consumer electronic applications. It comprises five members and provides 100000-1.6 million system gates. The Spartan-3e field-programmable gate arrays family builds on the previous family by increasing the logic per input/output number. It ends up reducing the cost for each logic cell significantly. The new features enhance the system performance and limit the configuration costs. Coupled with the advanced 90nm process technology, Spartan-3e delivers more bandwidth and functionality per dollar and thus sets new standards within the programmable logic industry.

The Spartan-3e FPGA family is a superior option to mask programmed ASICs and thus have wide-ranging applications in consumer electronics. It includes home networking, broadband access, and digital television and display equipment. So what important features should you consider when designing using these FPGAs?

Attributes

  • Low cost and high-performance logic solution for high-volume and consumer-oriented applications
  • Built on advanced 90nm process technology
  • Multi-standard and multi-voltage SelectIO interface pins
  • It includes 156 differential signal pin pairs or 376 I/O pins. It also has LVCMOS, HSTL, LVTTL, and SSTL single-ended signal standards. A five-option signaling including 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V with over 622 Mb/s data rates per input/output. Further, it also features DDR support and a DDR SDRAM support that reaches 333Mb/s.
  • This family has many flexible logic resources, including densities reaching 33192 logic cells, enhanced 18×18 multipliers, and a fast look-ahead carry logic.
  • It has a hierarchical SelectRAM memory architecture that reaches 648kbits of block random access memory and 231Kbits of effectively distributed RAM.
  • A maximum of eight DCMs (dual clock managers) featuring the elimination of clock skew, frequency synthesis, division, and multiplication, a wide-ranging 5MHz-300MHz frequency range, and high-resolution phase shifting. The DCMs offer fully digital and self-calibrating solutions for distributing, multiplying, delaying, and phase-shifting.
  • Eight global clocks beside another eight clocks for each half of the device. It also has plenty of low-skew routing.
  • The Spartan-3e FPGA possesses a configuration interface that aligns with industry-standard PROMs. It features a space-saving, low-cost SPI serial Flash PROM. It also has a low-cost Xilinx Platform Flash complete with JTAG.
  • The FPGA family possesses a WebPACK and ISE software
  • It has low-cost BGA and QFP packaging alternatives
  • Lead-free packaging alternatives
  • It demonstrates compliance with 32-/64-bit 33MHz PCI support and 66MHz support for some devices.
  • The common footprint enables simple density migration
  • Availability of XA automotive version   

Xilinx Spartan-3a FPGA Family

The Spartan-3a FPGA family solves plenty of challenges in a lot of high-volume and cost-sensitive applications. Equipped with twelve devices that range from 50000-3.4 million system gates, it provides a diverse range of package and densities alternatives. The number of system gates offers low overall system cost and an integrated DSP MAC while enhancing functionality.

The Spartan-3a comes as an extended family, and some of the constituents include Spartan-3a devices, Spartan-3AN DSP devices, and non-volatile Spartan-3AN devices. As such, the family FPGA enhances system performance and limits the configuration costs. The enhancements coupled with the 90nm process technology ensure extra bandwidth and functionality per dollar. The resulting low cost makes this family FPGA an ideal fit for diverse consumer electronic applications. Such applications include home networking, broadband access, digital television and display/projection equipment, etc.

Attributes

  • High-performance and low-cost logic solution for cost-conscious and high-volume applications
  • It primarily came about because of the fewer standard component utilization and increased system reliability.
  • Flexible power management with a low core voltage of 1.2V
  • It also has selectable five-option input/output voltages of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V for signaling. The dual-range secondary voltage permits a 3.3V setting which simplifies the 3.3V-only design. It also has the “hibernate” and “suspend” modes that reduce the system power consumption.
  • The Spartan-3a FPGA family also proves a leading connectivity platform helped by the multi-standard Select IO interface pin. It supports emerging and popular signaling standards. Additionally, it possesses a maximum of 227 differential signal pairs or 519 I/O pins. It has LVTTL, LVCMOS, SSTL, HSTL single-ended I/O. The family also features an enhanced DDR support, compliance with 32-/64-bit 33/66 MHz PCI tech, and a data transfer rate of above 640Mb/s.
  • Plenty of flexible logic resources with densities that go up to 53712 logic cells, including the alternative shift register
  • It also has effective wide multiplexers besides wide logic to enhance density and performance. Further, the fast look-ahead carry logic, and the IEEE 1149.1 JTAG debug/programming port enhances its capacity.  
  • The family has a dedicated resource for applications needing high-speed digital processing. It gets necessitated by the 18×18-bit multiplier with an alternative pipeline, 250MHz block in the largest devices.
  • Accurate clock management that has a maximum of eight DCMs
  • Some attributes include delay-locked loop or clock skew elimination, high-resolution phase shifting, frequency synthesis, division, and multiplication. It also features a broad frequency range of 5MHz-320MHz.

Other Vital Features

  • The family also has integrated flash memory, especially in the Spartan-3AN devices. Here the internal flash has a capacity of 16Mb for application storage and configuration. It also contains user storage of 11Mb for code shadowing, embedded processing, or scratchpad application. Such features make it possible to save space for single-chip board designs. It also improves the design security as it provides flash memory security complete with a security register.
  • This family has a hierarchical memory architecture (SelectRAM) with block RAM of up to 2.2 Mb with enabled byte-write for processor application. It also contains a maximum of 373 Kb for an effective distributed RAM and an external DDR SDRAM support that extends to 400 Mb/s.
  • The FPGA family also has a configuration interface that suits industry-standard PROMs. The configuration interface features aspects such as space-saving and low-cost SPI serial flash PROM, load multiple bitstreams under the control of the FPGA complete with multi-boot capability.
  • PicoBlaze and MicroBlaze embedded processors diminish obsolescence risks besides integrating soft processors into the FPGA to diminish the BoM.
  • Low-cost BGA and QFP packaging complete with lead-free alternatives
  • It also has a common footprint that supports a simple density migration.

Final Thoughts

Xilinx Spartan FPGA is an important product line that contains a lot more families than the ones discussed. However, within this product line, the families discussed are among the most important when considering low-cost and low FPGA footprint in the design of your processor. Consider the Spartan FPGA line, its various families, and their attributes to get started.