Zynq-7000 family of FPGAs have a lot of devices and Xilinx XC7Z020-1CLG484i is also one of them. These devices are built on the SoC architecture offered by Xilinx. The Zynq-7000 family is integrating abundant advanced features that its competitor devices lack. The device comes in either a single or dual-core ARM Cortex A-9 processor. The processing system of the device is grounded on the 28nm programmable logic introduced by Xilinx. The processing units are the integral part of the devices that also comprise built-in memory, interfaces for peripheral connectivity, and external memory.
The Xilinx XC7Z020-1CLG484i offers scalability and flexibility. It also delivers ease of use, power, and high performance that is associated with the ASSP and ASIC. These devices are very cost-sensitive and best suited to be used in higher performance applications from a common platform through the utilization of industry standards. Every device of the Zynq-7000 has input/output resources, PL, and PS but all features vary among devices depending on its use. There are abundant applications of Xilinx XC7Z020-1CLG484i and its family devices. For example, these devices are best to be used for driver assistance in the automotive industry, information delivery purposes to drivers, and in the infotainment of vehicles. These devices are preferred to be used in broadcasting cameras, motor control in industries, networking equipment of industries, and machine vision. The device is also utilized in smart and IP cameras. Recently, these devices were used in biomedical imaging and diagnostics, night vision, and video gadgets. Xilinx XC7Z020-1CLG484i is used in baseband and LTE radio sets and printers as well.
Interrupts and Timers
The device Xilinx XC7Z020-1CLG484i has numerous interrupts and timers. There is a controller for general interrupt. There are 3 watchdog timers i.e., each central processing unit has one watchdog timer. There are a couple of triple counters or timers. There is support offered for Cortex A-9 tracing and debugging of CoreSight. The device has a program trace macro-cell for tracing and instructions. The cross-trigger interface is enabling the device’s triggers and hardware breakpoints.
The Input/Output Peripherals of Xilinx XC7Z020-1CLG484i
The input/output peripherals or IOP unit of the device has peripherals for data communication. There are abundant key features of the IOP unit such as having a couple of tri-mode 10/100/1000 peripherals for ethernet MAC having IEEE 802.3 and 1588 revision 2.0 standards. This unit has the capability of scatter-gather DMA, recognition support for 1588 revision 2 frames, and a couple of USB 2.0 peripherals each with 12 endpoints. There is support for the PHY interface along with support for full-speed and high-speed modes in on-the-go, device, and host configurations. There is an external PHY interface as well along with a couple of UARTs. There are 2 SPI ports of full-duplex mode along 3 peripheral chip selects.
External Interfaces for PS
The external PS interfaces of Xilinx XC7Z020-1CLG484i are utilizing certain dedicated pins that PL pins could not be assigned with. Such pins comprise the voltage reference, clock, boot mode, and reset pins. There are over 54 multi-use input/output pins along with software configurable pins for connecting either of the internal input/output peripherals along with controllers for static memory.
Phase-Lock Loop and Mixed-Mode Clock Manager
MMCM or mixed-mode clock manager and PLL or phase-lock loop of Xilinx XC7Z020-1CLG484i have numerous characteristics. Both PLL and MMCM could be served as the synthesizer of frequency for a large frequency range and also as a filter for jitter for all of the incoming clocks. The voltage-controlled oscillator is lying in the middle of both MMCM and PLL which is pacing up or slowing down depending on the voltage at its input from the phase frequency detector. A total of 3 programmable frequency dividers are there, namely O, M, and D. D is known as the pre-divider reducing the frequency at its input and feeding one input of conventional PLL frequency/phase comparator. M is known as a feedback divider acting like a multiplier as it is divider the output frequency of VCO before it is fed to other inputs of the phase comparator. M and D must be selected appropriately as it keeps the VCO following the required range of frequencies. There are 8 phases at the output of VCO equally spaced by 45°. There are 3 input-jitter filtering options in PLL and MMCM i.e., mode of lower-bandwidth having best jitter attenuation, higher bandwidth mode having best phase offset, and an optimized mode having tools for detecting the best setting.
The PS of Xilinx XC7Z020-1CLG484i is equipped with 3 PLLs that deliver the required flexibility in the configuration of clock domains through the PS region. A total of three main clock domains exists within PS. These clock domains comprise peripherals for input/output, controllers for DDR, and APU. The software tool can be utilized for configuring the frequencies of all of the domains.
Software and Hardware Debug Support
The architecture of ARM CoreSight is utilized for the debug system of Xilinx XC7Z020-1CLG484i. This architecture is utilizing components of ARM CoreSight comprising of embedded buffer trace, macro-cell for program trace, and instrument trace macro-cell. This is enabling the features of instruction trace along with triggers and hardware breakpoints. An integrated analyzer for logic can also be utilized for debugging the programmable logic.
Power Modes of Xilinx XC7Z020-1CLG484i
There are numerous power modes offered by Xilinx XC7Z020-1CLG484i such as the sleep or programmable logic power-off mode. Both PL and PS are residing on various power planes and PS is capable of running with PL being powered OFF. However, for security purposes, PL could not be powered ON before PS. PL is requiring reconfiguration after every power-ON state. Therefore, the users are supposed to consider the configurations of PL time whenever utilizing the mode of power-saving. There is a PS clock control mode. PS is capable of running even in reduced clock rates at around 30MHz through the use of internal phase-lock loops. Therefore, the clock rate could be changed dynamically. For dynamically changing the clock, the users are supposed to unlock the control register of the system for accessing the control register of the PS clock. There is a single processor mode too in which the 2nd cortex A-9 central processing unit is in turned-OFF mode through the use of clock gating and the 1st central processing unit is kept in operational mode.