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Xilinx XC7Z010-2CLG400i FPGA Chip

The Xilinx XC7Z010-2CLG400i belongs to the Zynq-7000 series of devices. This device is available in various speed grades such as -1, -3, -1LI, and -2. The best performance is only with using -3 speed grade IC. The device of -1LI is capable of operating in a couple of programmable logic modes with its VCCBRAM or VCCINT to be 1.0V and 0.95V and are also separated for lower minimal static power. The specification of speed for -1 speed grade is identical to that of -1LI type speed grade. The dynamic and static power of the -1LI speed grade is reduced with it is operated in the VCCBRAM or VCCINT to be 0.95V.

The AC and DC characteristics of Xilinx XC7Z010-2CLG400i are categorized in different types such as expanded, commercial, industrial, extended, and defense temperature ranges. The only exception lies within the operational temperature range elsewhere, entire AC and DC electrical and electronic parameters are identical for all speed grade devices. Taking an example of the -1-speed grade device for industrial application has its timing characteristics identical to that of -1 speed grade devices used for commercial applications. Though, a specific range of devices are there for Q-temp, extended, industrial, and commercial ranges of temperature. The entire range of specifications for junction temperature and supply voltage is the representation of a worst-case scenario for the device. All of the included parameters are commonly considered for typical applications and popular designs.

Xilinx XC7Z010-2CLG400i PS Power Supply Sequence

For the device Xilinx XC7Z010-2CLG400i there is a specific powering ON sequence recommended by manufacturers starting with VCCPINT followed by VCCPAUX and VCCPLL and PS VCCO supplying power to VCCO_MIO0, VCCO_DDR, and VCCO_MIO1 for achieving minimal drawl of current and ensuring all of input/outputs to be the three-stated power ON stage. Whereas, the input of PS_POR_B is necessary for GND assertion during the power ON stage till VCCO_MIO0, VCCPAUX, and VCCPINT reach a minimal level of operation for ensuring the integrity of PS eFUSE. The preset setting of the device can be referred to when considering additional information regarding PS_POR_B timing.

The power OFF sequence for the Xilinx XC7Z010-2CLG400i as per the recommendation of its manufacturers is opposite to that of the power ON sequence. At a time when PS VCCO, VCCPLL, and VCCPAUX supplies are having an identical level of voltages, then all of these can get power through the same supply and can be ramped together as well. Xilinx is recommending delivering power to VCCPLL and VCCPAUX with one supply along with a ferrite bead filter. Beforehand, VCCPINT has reached the voltage of 0.80V, one of the conditions is required to be followed during the power OFF stage of the device. For example, the input of PS_POR_B is to be inserted to GND, the input of PS_CLK clock reference is to be disabled, VCCPAUX must be lower than 0.70V, or VCC_MIO0 is to be set at a value lower than 0.90V. Any of the aforementioned conditions must be set till the time when VCCPINT has reached a value of 0.40V for ensuring the integrity of PS eFUSE.

For the voltages of VCCO_MIO1 and VCCO_MIO0 to be 3.3V, the difference in voltage among VCCPAUX and VCCO_MIO1 or VCCO_MIO0 should not increase more than 2.625V for every Power ON/OFF cycle to maintain the level of reliability of the device Xilinx XC7Z010-2CLG400i.

Xilinx XC7Z010-2CLG400i PL Power Supply Sequence

The recommended PL power ON sequence for Xilinx XC7Z010-2CLG400i by manufacturers is to start with VCCINT followed by VCCBRAM, then VCCAUX, and end at VCCO for achieving minimal drawl of current to ensure the inputs/outputs to be in three-stated power ON state. Xilinx is recommending the power OFF sequence for the IC to be opposite to its power ON sequence. When VCCBRAM and VCCINT are having identical levels of voltages, then both of these could be powered with one supply and ramped together. For the voltages of VCCO to be 3.3V in configuration bank 0 and input/output bank, the difference of voltages among VCCAUX and VCCO should not be exceeding 2.625V for every power ON/OFF cycle for maintaining levels of reliability of the device.

GTP Transceivers

Xilinx XC7Z010-2CLG400i has a recommended sequence for its powering ON for achieving minimal drawl of current for its transceivers. The sequence starts with VCCINT, followed by VMGTAVCC, VMGTAVCC, or VMGTAVTT, then VCCINT, and ends at VMGTAVTT. VCCINT and VMGTAVCC both could be ramped together. Whereas, the powering OFF sequence recommended by Xilinx for the device is exactly opposite to its power ON sequence for achieving minimal drawl of current.

In case, if the recommended power ON/OFF sequences is not followed, then the drawn current from VMGTAVTT could be more than its requirements during its power ON/OFF cycle. At the time when VMGTAVTT is given power before VMGTAVTT-VMGTAVCC and VMGTAVCC are greater than 150mV and resultant VMGTAVCC is less than 0.7V but VMGTAVTT draws current with an increment of 460mA through every transceiver during the ramp-up of VMGTAVCC. The current drawl duration could be about 0.3 times VTMGAVCC. Whereas, its opposite procedure is true for its powering DOWN. At the time when VMGTAVTT is given power before VMGTAVTT-VCCINT and VCCINT are greater than 150mV and its VCCINT is less than 0.7V then its resultant drawl of current through VMGTAVTT could increment by 50mA through each transceiver while VCCINT is ramping up. The current drawl duration could also go up to 0.3 times VTCCINT. The opposite process is true for its powering DOWN.

Requirements of Power Supply

There are specific minimal current requirements for Xilinx XC7Z010-2CLG400i when it comes to powering ON of the device and its configuration setting. When minimal current requirements are fulfilled, the device is powered ON and all of its 4 PL power supplies get through their power ON threshold for voltages. The device should not be put in configuration mode till VCCINT is applied to it. Xilinx power estimator tool should be utilized after configuration and initialization for estimation of drain current on the supplies.

DC Output and Input Levels

The VIH and VIL values are recommended by Xilinx for input voltages of Xilinx XC7Z010-2CLG400i. Whereas, the values for IOH and IOL are assured for operating conditions that are recommended at testing points of VOH and VOL. Only specific standards are tested. The specific standards are supposed to be tested at a minimal value of VCCO along with its respective VOH and VOL level of voltages.