Integrated circuits are a vital aspect of electronic and electrical systems. It not only proves pivotal in designing electronics but ensures their proper functioning. Consequently, you will find ICs in amplifiers, computer memory, video processors, microprocessors, switches, etc. However, like all other industry-revolutionizing products and product lines, it is impossible to talk about and understand ICs fully without canvassing the Virtex FPGA. So what is it all about?
Virtex represents a flagship FPGA product family established by Xilinx. It includes models and configurations that are optimized for diverse applications. The Xilinx Virtex encompasses different families. It includes Virtex-E, Virtex-II, Virtex-4, Virtex-5, Virtex-6, and Virtex-7. Virtex-7 (3D), Virtex UltraScale, Virtex UltraScale+, and SoC finalize the product group.
Virtex FPGA series rely on the CLBs (configurable logic books). Each CLB equates to several ASIC gates and comprises several slices which have different construction architecture between families. Virtex FPGA also possesses other series, including Artix (low-cost), Kintex (mid-range), and Spartan low-cot series.
Virtex has diverse product series with plenty of families. Therefore, this article will focus on the Virtex FPGA product series. Let us get to it right away, shall we?
Xilinx Virtex FPGA
Virtex FPGAs from Xilinx have a huge industry reputation for their market impact and innovation. The Virtex FPGA gets programmed in special hardware description languages like Verilog or VHDL and utilizes the Vivado or Xilinx design suite. Its architectural design encompasses an I/O block that controls output and input pins in the Virtex chip. Such a design proves instrumental in supporting a myriad of signaling standards.
All the pins are the default for the input mode, implying high impedance, with I/O pins getting assembled into I/O banks that feature every bank supporting a different voltage. Moreover, besides configurable FPGA, the Virtex FPGAs also entail fixed-function hardware for memories, multipliers, microprocessor cores, ECC, and FIFO logic, besides DSP bocks. But it does not stop there; it encompasses Ethernet high-speed serial transceivers, MAC blocks, and PCI express controllers.
If you, therefore, need to purchase a Virtex FPGA product series from Xilinx, it helps to consider certain aspects. For instance, it will come in handy to comprehend the different series for each product line under the Xilinx Virtex FPGA product line, their corresponding features, and their suitability to your area of application. Additionally, other aspects such as costs, your PCB contract manufacturer, PCB design needs, etc., have to be factored in.
Xilinx Virtex-II
The Virtex-II FPGA family was developed for high-performance functions encompassing low to high-density designs and basing everything on its customized modules and IP cores. It delivers a comprehensive solution for wireless networking, telecommunication, DSP, and video applications. It entails DDR, LVDs, and PCI interfaces. The advanced Virtex-II architecture, besides the 0.15 µm / 0.12 µm CMOS 8-layer metal procedure, ensures optimization for low-power, high-speed operations. Additionally, it combines many flexible attributes and densities that go up to ten million system gates. Consequently, it reinforces programmable logic design abilities besides proving a fantastic option in mask-programmed arrays.
- Input/Output Blocks
The IOBs prove programmable besides having three categorizations. It includes an input block complete with DDR or single-data-rate register, output block with DDR register, and a bidirectional block combining output and input configurations.
- CLBs
It is a resource that encompasses two 3-state buffers and four slices. Each has two function generators, arithmetic logic gates, two storage elements, a fast carry look-ahead chain, large multiplexers, a horizontal cascade gate, and extensive function ability.
- Global Clocking
The global clock multiplexer and DCM buffers give a comprehensive solution in the design of high-speed clocking schemes. The Virtex-II possesses up to twelve DCM blocks, with every DCM capable of being deployed to eradicate clock distribution delays.
- Routing Resources
All the Virtex-II elements, such as CCLB, IOB, etc., use a similar interconnect scheme with a single global routing matrix access. A total of sixteen global clock lines exist, with each quadrant having eight.
- Configuration
Virtex-II devices get configured through a process of loading data to the internal configuration memory. It uses one among the five: slave-serial, slave selectMAP, master-serial mode, master SelectMAP, and boundary-scan modes. Additionally, a DES (Data Encryption Standard) decryptor proves available.
Xilinx Virtex-2Pro
It comes as an FPGA design based on customized modules and IP cores. The Virtex-II Pro adds a PowerPC CPU and multi-gigabit transceiver in its architecture. Therefore, it offers a comprehensive solution to wireless, telecommunication, video, wireless, DSP, and networking applications. The industry-leading 0.13 µm CMOS nine-layer copper process, besides the Virtex-II Pro architecture, ensures optimization for high-performance designs featuring a divergent density range. Additionally, it mixes a myriad of IP cores and flexible attributes, which enhance the programmable logic design abilities. Consequently, it is an excellent option to mask programmed gate arrays.
- IOBs
The input/output blocks come programmable and with diverse categorizations. The registers prove level-sensitive or edge-triggered D-type flip-flops latches. What’s more? The IOBs support single-ended I/O standards like LVCMOS and LVTTL, PCI-X compatible, PCI compliant, and GTLP and GTL compliant.
- PowerPC 405 Processor Block
The PPC405 RISC CPU executes instructions at sustained rates of a single instruction per cycle. Additionally, data cache and on-chip instruction limit design complexity besides enhancing system throughput. Features include storage control, PowerPC RISC CPU, a virtual memory management unit, debug support, and OCM controllers.
- CLBs
The configurable logic blocks possess two 3-state buffers and four slices. Each slice proves equivalent to the next and has two function generators, arithmetic logic gates, two storage elements, large multiplexers, a Horizontal cascade gate or chain, and wide function ability. Here, the function generators also prove configurable.
- Routing Resources
Elements such as the CLB, IOB, block SelectRAM+, DCM, and multipliers utilize one scheme besides a similar global routing matrix. Timing models also get shared, and this improves the predictability aspect of high-speed design performance.
- Configuration
It proves similar to all other Virtex families, especially on the mode of bitstream loading. However, the DES ensures the security of the bitstream once loaded on the chip.
- Integrated Logic Analyzer and Readback
Another key element of the Virtex-II pro is that its stored configuration data can be read back in instances requiring verification. Consequently, it allows for a seamless debugging process whenever necessary.
Xilinx Virtex-4
Similar to other Virtex series, the Virtex-4 from Xilinx combines the ASMBL architecture with a wide-ranging variety of flexible attributes. It enhances the programmable logic design abilities, ranking it a powerful option to the ASIC tech. Virtex-4 FPGAs encompass three subfamilies in LX, SX, and FX and thus provides multiple attribute options and combinations that can address complex applications. It has a hard-IP core block encompassing the PowerPC processors, 622 Mb/s to 6.5 Gb/s serial transceivers, tri-mode Ethernet MACs, dedicated DSP slices, source-synchronous interface blocks, and high-speed circuitry in its clock management. A standard Virtex-4 FPGA building block improves the ones found in renowned Virtex, Virtex-E, Virtex-II Pro, Virtex-II, and Virtex-II Pro X families. Therefore, it implies that earlier generation designs can prove upward compatible.
The Virtex-4 devices get fabricated on an advanced 90nm copper procedure by deploying 300 mm wafer technology.
- Configuration
Virtex-4 devices get configured through a loading process of the bitstream to the ICM or internal configuration memory. It completes this through slave-serial, master SelectMAP, slave selectMAP, master-serial, and boundary-scan mode. It also features an optional 256-bit AES decryption that gets supported on-chip. Consequently, it provides intellectual property (IP) security.
- Block RAM
It has a block RAM resource of 18 Kb true dual-port RAM, and it is programmable from 16K x 1 to 512 x 36, width and depth configurations. Additionally, every port is fully independent and synchronous. It thus offers three “read-during-write” modes. What’s more? Block RAM proves cascadable and should carry out large embedded storage blocks. Further, the back-end pipeline register, built-in FIFO support, byte write, and clock control circuitry prove but only a few features supported within the Virtex-4 FPGA
- CLBs
For the Virtex-4 FPGAs, the CLB resource comprises four equivalent slices. Each has two function generators, arithmetic logic gates, two storage elements, and larger multiplexers, besides a quick carry look-ahead chain. The Virtex-4 FPGA’s function generators prove configurable as 4-input LUTs. Two CLB slices can get their LUTs configured to become 16-bit distributed RAM or 16-bit shift registers. Its two storage elements can also prove level-sensitive or edge-triggered D-type flip-flops latches.
- I/O Blocks
Input/output blocks come programmable with different categorizations. Further, the IOB registers can either prove level-sensitive latches or edge-triggered D-type flip-flops. Another possibility entails configuring the DCI I/O attribute to offer on-chip termination, especially for every single-ended I/O and differential I/O standard.
- Routing Resources
Components on the Virtex-4 devices deploy a similar interconnect scheme besides a similar global routing matrix access. Additionally, the timing models get shared and thus, enhances the performance prediction for the high-speed designs.
Xilinx Virtex-5
The Virtex-5 FPGAs deploy the second-generation ASMB column-based architecture. It possesses five sub-families, with every sub-family having a distinct features ratio regarding meeting the needs of diverse and advanced logic designs. The FPGA family contains the most progressive, high-performance logic fabric. It also has plenty of hard-IP system-level blocks that include the powerful 36-Kbit block RAM and second-generation 25 x 18 DSP slices. It also contains the SelectIO technology (including built-in digitally-controlled impedance), system monitor functionality, and the ChipSync source-synchronous interface blocks. Further, the Virtex-5 FPGA also features a superior clock management tile complete with an integrated PLL and DCM clock, innovative configuration options, and generators.
- Configuration
The Virtex-5 devices get configured through a bitstream loading process into the internal configuration memory. It can become a reality through the deployment of the following modes. The slave-serial, master-serial, slave selectMAP, master SelectMAP, boundary-scan, SPI, and BPI-down/BPI-up modes. Additionally, it supports options such as 256-bit AES bitstream decryption, multi-bitstream management, and the auto-detection of the parallel configuration bus width. What’s more? It can also support parallel daisy chains and ECC and CRC configurations.
- System Monitor
The system monitor on the Virtex FPGAs from Xilinx is a vital building block for high reliability or availability infrastructure. It enhances the monitoring of the on-chip FPGA physical environment besides its immediate system surroundings. It has several subfamilies, with each member possessing a system monitor block. The Virtex-5 System Monitor is built using a 10-bit 200kSPS Analog-to-Digital Converter (ADC).
An ADC is instrumental in digitizing several on-chip sensors in providing information concerning the FPGA’s physical environment. The on-chip sensors entail a power supply and temperature sensors. External environmental access gets facilitated by several external analog input channels. Such analog inputs come general purpose and, thus, can get deployed in digitizing a diverse variety of voltage signals.
In addition, support gets provided for true differential, bipolar, and unipolar input schemes. Consequently, full access to external channels and on-chip sensors is guaranteed through the JTAG TAP, which allows the present JTAG infrastructure located on the board (PC) to be utilized for advanced diagnostic and analog tests during development and post-deployment. The System Monitor often proves fully operational before the FPGA configuration and after powering it up. Further, the System Monitor never needs an obvious instantiation in the design to access aspects such as basic functionality. Consequently, it permits the System Monitor utilization during the latter stages of the design cycle.
- Routing Resources
Every component in the Virtex-5 device deploys a similar interconnect scheme besides single access to the universal routing matrix. Additionally, the design of the CLB-to-CLB routing provides a comprehensive connectivity set in very few hops. Since timing models get shared, the prediction of the high-speed designs gets enhanced.
- Global Clocking
The global-clock multiplexer buffers and the CMTs offer a comprehensive solution for the design of high-speed clock networks. Every CMT possesses a single PLL and two DCMs. The PLL and DCM can be deployed independently. The Virtex-5 contains up to six CMT blocks and thus offers a total maximum of eighteen clock generator elements. Each DCM gives a familiar clock generation ability. However, when it comes to the generation of deskewed external or internal clocks, every DCM can get utilized to eliminate the delay in clock distribution. It also offers 270°, 180°, and 90° phase-shifted output clock versions. The Virtex-5 FPGA has PLL to augment the capability of the DCM. Such a clock offers extra synthesis and reference clock jitter filtering options. What’s more? It possesses 32 global-clock MUX buffers complete with a differential clock tree to minimize the duty cycle distortion besides the jitter.
- Boundary Scan
The boundary-scan associated data registers and instructions support a typical configuration and access methodology for Virtex-5 devices. Consequently, it allows for conformation and compliance with IEEE standards 1532 and 1149.1.
- Block RAM
The Virtex 36 Kbit, dual-port RAM block resources, come programmable, especially from 32K x 1 to 512 x 72, in diverse width and depth configurations. Additionally, every 36-Kbit block can get configured to function as two autonomous 18-Kbit dual-port RAM blocks. Remember, every port is fully independent and synchronous and thus provides three “read-during-write” modes.
- CLBs
The configurable logic block resource entails two equivalent slices. Every slice has four storage elements, a similar number of function generators, large multiplexers, arithmetic logic gates, and a quick carry look-ahead chain. The function generators can get configured as dual-output 5-input or 6-input LUTs. Additionally, the storage elements (four) can get configured into level-sensitive or edge-triggered D-type flip-flop latches.
- I/O Blocks
The Virtex-5 FPGAs have programmable IOBs with diverse categorizations. The DCI (digitally controlled impedance I/O attribute can get configured to give on-chip termination.
Xilinx Virtex-6 FPGA
The series comes as a programmable silicon foundation for TDPs (targeted design platforms) to deliver integrated hardware and software components. Consequently, it enables designers to concentrate on innovation immediately after their cycle of development starts. The series deploy the ASMBL column-based architecture besides possesses several individual sub-families.
It has countless built-in system-level blocks. Such attributes allow the logic designers to develop the highest functionality and performance levels in the FPGA-based system. The Virtex-6 FPGA gets built using the 40 nm cutting-edge copper process tech. It also proves a programmable option when it comes to custom ASIC tech. Virtex-6 FPGA provides a top solution in addressing the requirements of high-performance DSP, logic, and embedded system designers, primarily those with unprecedented connectivity, logic, soft microprocessor, and DSP capabilities.
- Configuration
Virtex-6 FPGA has a customized configuration and stores it in an SRAM-type internal latch. The configuration bits can range from 26Mb to 177Mb based on the device’s size but disregard the particular user-design implementation unless you deploy the compression mode.
Additionally, the configuration mode proves volatile and requires reloading every time the FPGA gets powered up. It is possible to reload this storage at any moment, provided you pull the PROGRAM_B pin low.
Bit-serial configuration can come as either master serial mode or the slave serial mode. The master serial mode infers when the FPGA creates the CCLK signal, while the slave serial mode implies when the external configuration source of data clocks the FPGA. A standard configuration process encompasses the execution of the sequence as follows.
- It detects power-up or PROGRAM_B during Low
- It clears the entire configuration memory
- A sampling of the mode pins gets completed to establish the configuration mode. It can prove slave or master, parallel or bit-serial, or even bus width.
- It loads the configuration files and begins with the bus-width detection pattern, synchronization word, checking for the correct device code before ending with the CRC (cyclic redundancy check) of the whole bitstream.
- Start-up then implements a user-defined events sequence that releases the internal presser or reset of flip-flops, optionally waits for the PLLs or phase-locked loops to lock or/and the matching of the DCI, besides activating the drivers’ output, and transitioning the DONE pin to High.
- CLBs, LUTs, and Slices
It is possible to configure the LUT (look-up table) of Virtex-6 FPGAs as either two 5-input LUTs with isolated outputs but possessing common addresses or one 6-input LUT with a singular output. Optional registration of every LUT output can get carried out in a flip flop. Consequently, four such LUTs, together with their arithmetic, carry logic form, multiplexers, two slices, and eight flip flops from the CLB. It is also possible to optionally configure four flip flop slices as latches, provided that you configure each flip flop slice per LUT. However, such an occurrence demands that the rest (four flip-flops in the slice) stay unused.
- Clock Management
Every Virtex-6 FPGA contains up to nine CMTs (clock management tiles), each comprising two MMCMs (mixed-mode clock managers) that prove PLL-based. It features attributes such as phase-locked loop, MMCM programmable features, and clock distribution.
- Block RAM
Every Virtex-6 FPGA contains a range of 156 to 1064 dual-port block RAMs. Remeber, each port block stores 36 Kbits. Additionally, each RAM block possesses two independent ports with nothing in common other than the data stored. It features synchronous operation, error detection, and rectifier, besides a programmable data width.
- Digital Signal Processing
DSP applications deploy numerous binary accumulators and multipliers, best executed in devoted DSP slices. Every Virtex-6 FPGA has plenty of dedicated, low-power, and full-custom DSP slices, and these combine small size with high speed while retaining the flexibility of the system design.
- I/O (Input/Output)
The amount of I/O pins differs and can range from 240 to 1200 based on the package size and device. Every I/O pin can get configured to comply with a hefty amount of standards. Besides the supply pins and other dedicated configuration pins, every package pins possess similar I/O capabilities that can only get constrained by specific banking rules.
I/O pins get organized in banks of forty pins. Each bank contains one standard output supply-voltage pin that powers specific input buffers. An important consideration for I/O pins includes understanding their electrical characteristics, digitally controlled impedance, and corresponding I/O logic.
- System Monitors
All Virtex-6 FPGAs have system monitor circuits that provide power supply and thermal status information. The sensor outputs get digitized with a 10-bit 200kSPS ADC. The system monitor by design consistently digitizes all the on-chip sensors output. Every recent reading (measurements) gets stored in devoted registers.
It is vital to note that the series does not end at the Xilinx Virtex-7. Other families within this product line exist and include Virtex-7 FPGA, Xilinx PROM, etc., to mention but a few.
Conclusion
Integrated circuits are vital for electronic systems and so do the Xilinx Virtex product lines. If you want to buy a relevant IC within this product range but are unsure what to settle for, you can always get guidance at RayMing PCB and Assembly. Customer care is one among many IC services we provide.
Xilinx Virtex Part Numbers List
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