Field Programmable Gate Arrays (FPGAs) are integrated circuits that can be programmed and reconfigured by the user after manufacturing. This makes them a flexible and powerful option for digital circuit implementation. While hobbyists typically use commercial FPGAs from vendors like Xilinx and Intel (Altera), it is possible to design your own FPGA as well. This article will provide an overview of the key steps involved in custom FPGA design.
Overview of FPGA Architecture
To understand how to design an FPGA, we first need to understand the high-level architecture. A basic FPGA consists of the following key components:
Configurable Logic Blocks (CLBs) – These are the basic logic units whose functions can be programmed. CLBs include lookup tables (LUTs) and flip-flops.
I/O Blocks – Provide the interface between the I/O pins and internal programmable logic. Support various I/O standards.
Clock Circuitry – Includes clock buffers, PLLs, DLLs to drive clock networks across the FPGA.
Memory and DSP Blocks – Some FPGAs include dedicated blocks of RAM, ROM and DSP slices.
Configuration Memory – Stores the programming that defines the FPGA functionality. Volatile or non-volatile.
PCIe, Ethernet, etc. – Some FPGAs have hard cores for various interfaces integrated on-chip.
Processor Cores – Modern FPGAs may include embedded ARM cores for SoC applications.
This architecture with flexible programmable logic, routing and I/O provides the foundation for an FPGA that can be customized by designers.
FPGA Design Flow Overview
Designing an FPGA from scratch involves several steps that can be grouped into two main phases:
1. Design and Verification
This involves using HDLs like VHDL or Verilog to design, simulate and verify the functionality of the various FPGA blocks at the register-transfer level (RTL). EDA tools like Quartus from Intel or Vivado from Xilinx are leveraged for synthesis and simulation. Reusable IP cores may be purchased for some functions.
Once RTL models of the FPGA fabric are finalized, gate level netlists are generated, checked for logical equivalence against RTL and timing analysis is done to meet speed goals.
2. Physical Implementation
The gate level netlist is then taken through the physical design stages of floorplanning, place-and-route, timing closure, and tapeout. Electronic design automation (EDA) tools automate mapping the netlist to actual gates and transistors on silicon but manual optimization is required.
The final tapeout is the complete database (GDSII stream format) defining the photolithographic masks to manufacture the FPGA. This is sent to a silicon foundry like TSMC for fabrication.
This overall flow requires expertise in digital logic design, HDL modeling, ASIC/FPGA architecture and semiconductor fabrication. Let’s look at each major step in more detail.
Detailed FPGA Design Steps
Here are the specifics of designing and implementing an FPGA from concept to final silicon:
1. Concept Development
- Define target device capabilities and applications. Factors like logic cells, speed, power, cost, and features impact architecture decisions.
- Specify high-level functional requirements. Example: “The FPGA should support 250K logic cells, 200 MHz speed and DDR3 memory interface”.
- Plan top-level architecture – logic blocks, routing channels, I/O count, clocking, embedded IP cores etc.
- Evaluate commercial IP cores that can be licensed to reduce design effort for standard functions.
2. Feasibility Study
- Research existing open literature and patents around similar architectures.
- Create silicon area and power rough estimates for planned architecture.
- Estimate expected timing performance based on planned process node.
- Assess if performance targets can realistically be met within area and power budget.
- Refine architecture if needed based on feasibility study results.
3. RTL Functional Design
- Use Hardware Description Languages like VHDL or Verilog to model the following FPGA modules at the RTL level:
- Configurable Logic Blocks (CLBs)
- Input/Output Blocks (IOBs)
- Programmable Interconnect
- Clocking resources
- Memory/DSP blocks
- Configuration memory
- Any other logic blocks
- Verify functionality by simulating RTL modules/subsystems. Develop testbenches to validate operation.
- Iterate modules as needed till functionally correct.
4. Synthesis and Gate-Level Simulations
- Perform logic synthesis to convert RTL models into technology-mapped gate-level netlists.
- Verify netlists match RTL functional behavior via gate-level simulation.
- Run equivalency checking to formally verify logical equivalence of netlists vs RTL code.
- Iterate until netlists match RTL functionality and are logically equivalent.
5. Static Timing Analysis
- Perform static timing analysis on gate-level netlist using timing constraints.
- Identify critical timing paths that need optimization to meet clock frequency target.
- Modify RTL and re-synthesize to close timing if needed.
- Sign-off on timing closure when all paths meet timing goals with margin.
- Determine the relative placement of FPGA blocks on the die based on connectivity and shape.
- Decide aspect ratio and pin locations.
- Allocate space for routing channels between blocks.
- Ensure good floorplan to optimize timing, routability and die area.
7. Power Planning
- Estimate power consumption of logic blocks and I/Os.
- Plan power grid distribution across the die to provide clean power to cells.
- Insert power gating cells or switches if needed to control power.
- Add voltage islands if required for low power modes.
8. Place and Route
- Automatically place logic gates and cells within each FPGA functional block.
- Route interconnect wires between cells following electrical and timing constraints.
- Verify all connections meet physical design rules for width/spacing.
- Iterate optimizations to meet timing closure and minimize wirelength.
9. Physical Verification
- Run design rule checks for errors like minimum spacing or overlaps between shapes and layers.
- Verify layout versus schematic matching.
- Extract parasitics and redo timing analysis to validate performance.
- Perform formal verification on final routed layout.
- Signoff physical verification when the tapeout database passes all checks.
- Generate final GDSII layout database containing mask layers to send for fabrication.
- Include other deliverables like LEF, Liberty timing models, CDL netlist, etc.
- Perform manufacturability checks like DFM analysis.
- Submit tapeout data to foundry like TSMC for mass production.
With these steps complete, the FPGA design is fabriccated into actual silicon chips that can be programmed by designers!
Challenges in Custom FPGA Design
While the design flow seems straightforward, creating a custom FPGA from scratch poses several tough challenges:
- Achieving timing closure across P&R, synthesis and physical optimization is extremely difficult given the complexity.
- Router has to implement programmable interconnects with an enormous solution space.
- Strict silicon area targets for optimal transistor density and die yield.
- Power grid has to provide very clean power across the die.
- Thorough simulation and verification requires exhaustive testbenches.
- Fabrication process tolerances can affect performance.
- Requires large, experienced, multi-disciplinary engineering teams.
- Total design cost can easily reach tens of millions of dollars.
Because of these challenges, custom FPGA startups require substantial financial backing to design competitive products. Leveraging existing FPGA vendor solutions or licensing their IP can help mitigate technical risks and costs.
When Does Custom FPGA Design Make Sense?
Given the high costs, effort and risks involved, developing a custom FPGA device from scratch is only justified for a few specific applications:
- Building differentiated FPGA products for a niche application space not served well by existing vendors. Eg. radiation-hardened FPGAs.
- Merging an FPGA with other silicon IPs like processors, SerDes, analog, etc. to create a highly integrated system-on-chip solution.
- Implementing novel FPGA architectures for research purposes to push new ideas in academia.
- Developing strategic advantage in critical domains like aerospace, defense or high-end computing where competitive edge in programmable chips is valued.
For most commercial applications, licensing proven FPGA technology from Xilinx, Intel or others and customizing the design on top offers a faster time-to-market with lower risk.
Options for FPGA Design Without Fabricating Silicon
For hobbyists, researchers, or smaller teams with limited budgets, there are options to design and validate custom FPGA architectures without having to actually fabricate the chip which requires millions of dollars:
FPGA Prototyping Boards
- Prototyping boards like the Xilinx Virtex-7 or Intel (Altera) Stratix-10 allow implementing and testing FPGA architectures using their programmable fabric.
FPGA Emulation on FPGAs
- Using HLS or HDLs, the architecture of a novel FPGA can be modeled and functionally verified by mapping it onto an existing physical FPGA.
FPGA Simulation Environments
- Computer-based simulations of FPGA fabrics using HDL testbenches and tools like ModelSim can be created to evaluate new architectures.
Rapid Prototyping Using CPLDs
- For limited logic capacity testing, Complex Programmable Logic Devices (CPLDs) provide an easier and cheaper alternative to prototype concepts.
Cloud-based FPGA Resources
- Xilinx and Intel provide cloud-based access to FPGAs that can be leveraged for experiments before committing to silicon fabrication.
While not exactly the same as taping out real custom silicon, these options allow flexibility for innovators and startups to validate their ideas without prohibitive fab costs.
Open Source FPGA Projects
For reference, there are some open-source projects that aim to provide free and customizable FPGA platforms:
- Symbiflow – Toolchain for developing open-source FPGAs.
- LiteX – Migen and LiteX ecosystem for building FPGA-based systems.
- OpenFPGA – Open-source framework for developing FPGA architectures.
- GreenArrays – Ultra low-power open FPGA architecture.
- Kiwi – Educational miniature FPGA board designed in New Zealand.
While full-custom FPGA design requires substantial expertise and effort, these open initiatives help democratize access to FPGA technology for hobbyists.
Designing a custom FPGA device from the ground up is a complex process requiring advanced engineering expertise across RTL design, EDA tools, architecture, physical implementation, and fabrication. While challenging, for specific applications like IP differentiation, research or vertical integration, a custom-designed FPGA can provide strategic benefits. For most purposes, however, leveraging existing proven FPGA technology and IP from vendors like Xilinx and Intel provide the best trade-offs. The emergence of open-source FPGA tooling and platforms is also making FPGA customization more accessible to innovators.
Top 5 FAQs about FPGA Design
Here are some frequently asked questions about designing your own custom FPGA:
Q1: What expertise is required for full-custom FPGA design?
A: You need digital design engineers proficient in RTL coding (VHDL/Verilog), FPGA architects, physical design engineers, verification specialists, and semiconductor process technology know-how.
Q2: What kind of budget is needed for a new FPGA tapeout?
A: The cost can range from $10M to $50M+ for a new full-custom FPGA depending on the complexity, process node, tool licenses, engineering team size etc.
Q3: How long does it take to design and tapeout an FPGA?
A: For a reasonably complex FPGA architecture with all the steps done rigorously, the entire process typically takes 12-18 months from concept to final tapeout database.
Q4: Can I modify an existing FPGA without taping out new silicon?
A: Yes, you can customize existing FPGA designs using HDL overrides, IP integration, partial reconfiguration etc. without having to create a brand new device from scratch.
Q5: Is open source FPGA technology mature enough for commercial use?
A: Open-source FPGA tooling provides a great learning platform but still has limitations in the complexity of designs possible compared to Cadence/Synopsys/Mentor commercial EDA tools.