Quick Presets

Layer Assignment (SIG-GND-SIG-PWR Pattern)
L1 SIG
L2 GND
L3 SIG
L4 PWR
L5 SIG
L6 GND
L7 PWR
L8 SIG
L9 GND
L10 SIG
L11 PWR
L12 SIG

Copper Layers (12)

Prepreg Layers (6)

Core Layers (5)

Total Board Thickness
2.000mm
2000 ยตm
vs 2.0mm
+0 ยตm
Copper (12L)
420 ยตm
Prepreg (6L)
826 ยตm
Core (5L)
800 ยตm

Stackup Visualization

L1 – Top SignalSIG 35ยตm
PP1 114ยตm
L2 – GND PlaneGND 35ยตm
Core 1 100ยตm
L3 – SignalSIG 35ยตm
PP2 114ยตm
L4 – PWR PlanePWR 35ยตm
Core 2 200ยตm
L5 – SignalSIG 35ยตm
PP3 185ยตm
L6 – GND PlaneGND 35ยตm
Core 3 (Center) 200ยตm
L7 – PWR PlanePWR 35ยตm
PP4 185ยตm
L8 – SignalSIG 35ยตm
Core 4 200ยตm
L9 – GND PlaneGND 35ยตm
PP5 114ยตm
L10 – SignalSIG 35ยตm
Core 5 100ยตm
L11 – PWR PlanePWR 35ยตm
PP6 114ยตm
L12 – Bottom SignalSIG 35ยตm
SOLDER MASK (BOTTOM)
Outer Signal
Inner Signal
GND Plane
PWR Plane
Prepreg
Core
๐Ÿ’ก Common 12-Layer Targets
1.6mm: High-density HDI designs
2.0mm: Standard 12L (most common)
2.4mm: Server, networking
3.0-3.2mm: Backplanes, heavy copper
๐Ÿ“ Impedance Zones
Microstrip: L1โ†’L2, L12โ†’L11
Stripline: L3, L5, L8, L10
Broadside: L6โ†”L7 (tight coupling)
โšก 12-Layer Design Strategy
6 Signal Layers: L1, L3, L5, L8, L10, L12 โ€” Maximum routing density with 4 protected stripline layers.
3 GND Planes: L2, L6, L9 โ€” Distributed ground reference minimizes return path inductance.
3 PWR Planes: L4, L7, L11 โ€” Multiple power domains with L6-L7 forming a low-inductance decoupling pair.
Symmetry: Structure is symmetric about center for optimal warpage control during reflow.