4 Rules of Designing Circuit Width and Spacing

4 Rules of Designing Circuit Width and Spacing with impedance control

 

1. The signal circuit that needs to do impedance should be set strictly according to the circuit width and circuit spacing calculated by the stack-up. For example, Radio frequency(RF) signal ( conventional 50R control), important single-ended 50R, differential 90R, differential 100R and other signal circuit, through the stack-up can calculate the specific circuit width circuit spacing (pictured below).

 

Stack up of Single Trace and Differential Trace Impedance Control

 

2. The circuit width and circuit spacing of the design should consider the production process capability of the selected PCB production factory. If the circuit width and circuit spacing are designed to exceed the process capability of the cooperating PCB manufacturer, it is light to add unnecessary production costs. It is serious that causes the design to fail to produce. Under normal circumstances, the circuit width is controlled to 6/6mil, and the via is 12mil (0.3mm). Basically, more than 80% of PCB manufacturers can produce it with the lowest cost.

 

The circuit width is controlled to a minimum of 4/4mil, and the via is 8mil (0.2mm). Basically, more than 70% of PCB manufacturers can produce it, but the price is slightly more expensive than the first case, not too expensive. The circuit width is controlled to a minimum of 3.5/3.5mil, and the via is 8mil (0.2mm). At this time, some PCB manufacturers can't produce it, and the price will be more expensive. The circuit width is controlled to a minimum of 2/2mil, and the via is 4mil (0.1mm, which is usually a HDI blind buried hole design, which requires laser via).

 

At this time, most PCB manufacturers can't produce the price, which is the most expensive. of. The circuit width circuit spacing here refers to the size between the circuit to the hole, the circuit to the circuit, the circuit to the pad, the circuit to the via, the hole to the pad and something like that.

 

3. Set the rules to consider the design bottlenecks in the design file. If there is a 1mm BGA chip, the pin depth is shallow, only one signal circuit needs to be taken between the two rows of pins, which can be set 6/6mil, the depth of the pin is deep, and two pins need to be taken between the two rows of pins. The signal line is set to 4/4mil; there is a 0.65mm BGA chip, which is generally set to 4/4mil;There is a 0.5mm BGA chip, the minimum circuit width must be set to 3.5/3.5mil; the 0.4mm BGA chip generally needs to be HDI design. Generally, for the design bottleneck,

 

the area rule can be set (for the setting method, see the end of the article [AD software setting ROOM, ALLEGRO software setting area rule]) , the local circuit width is set to a small point, and the other rules of the PCB are set larger for production. Improve the PCB pass rate.

 

4. We need to be set according to the density of the PCB design, the density is small, the board is loose, the circuit width can be set larger, and vice versa. General can be set by the following steps:

 

1) 8/8 mil, 12 mil (0.3 mm) via.

2) 6/6mil,12mil(0.3mm)via。

3) 4/4 mil, 8 mil (0.2 mm) via.

4) 3.5/3.5 mil, 8 mil (0.2 mm) via.

5) 3.5/3.5 mil, 4 mil (0.1 mm, laser perforation) for via.

6) 2/2 mil, 4 mil (0.1 mm, laser perforation) for via.