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How to Design pcb trace spacing and Width ?


Properly designing trace spacing and widths is critical when laying out printed circuit boards. Together, these parameters impact current carrying capacity, impedance, noise, manufacturability, and signal integrity. Insufficient spacing or improper trace widths can lead to short circuits, crosstalk, excessive EMI, and other issues degrading circuit performance.

This article provides guidance on how to select appropriate PCB trace spacing and widths based on current levels, voltage, impedance targets, noise minimization, and fabrication capabilities. Design examples along with spacing and width determination procedures are also provided.

Trace Spacing Basics

Trace spacing refers to the distance between adjacent PCB traces on a given layer. Key considerations when setting trace spacing include:

  • Isolation – Prevent short circuits between closely spaced high voltage traces.
  • Crosstalk – Minimize interference between neighboring traces, especially for fast switching digital or RF traces.
  • Impedance – Spacing impacts achievable trace impedance based on capacitive coupling.
  • Current – High current traces require larger spacings to prevent voltage arcing.
  • Manufacturability – Accommodate tolerances of fabrication processes.
  • Repairability – Provide adequate spacing for rework, solder mask repair, or trace cuts.
  • Routing Density – Tighter spacings allow greater layout density.

Balancing these considerations determines optimal trace-to-trace spacing.

Trace Width Basics

PCB Claculator Trace Width
PCB Claculator Trace Width

Trace width is the cross-sectional width of a conductive copper track. Key factors influencing width selection include:

  • Current Rating – Wider widths increase current carrying capacity.
  • Impedance – Narrower traces yield higher impedances.
  • Thermal Relief – Thicker traces help conduct heat from high power components.
  • Etching – Size limits set by minimum manufacturable widths and tolerances.
  • Reliability – Thicker traces are more robust to breaks or damage.
  • Cost – Thinner traces reduce copper usage and improve yield.
  • EMI – Narrower traces radiate less electromagnetic interference.

Selecting trace widths requires assessing electrical current needs, impedance targets, thermal loads, manufacturability, and cost impact for optimal results.

Trace Spacing Design Rules

Here are some typical design rules used when setting PCB trace spacing:

Based on Voltage

Higher voltage traces require larger spacing to prevent arcing. Common design rules:

Trace-to-Trace VoltageMinimum Spacing
< 50V2x trace width
50-150V3x-4x trace width
150-300V5x-8x trace width
>300V10x+ trace width

Based on Impedance

Wider spacing lowers capacitive coupling, increasing impedance. Examples:

Target ImpedanceSpacing
50 Ohms1x-2x trace width
75 Ohms2x-3x trace width
90-100 Ohms3x-4x trace width

Based on Crosstalk Prevention

Larger spacings between high speed digital or analog traces minimize noise coupling:

Trace TypeSpacing
Digital signals > 50MHz>4x trace width
RF/microwave traces>5x trace width
Sensitive analog signals>3x trace width

Based on Manufacturability

Accommodate fabrication process capabilities and tolerances:

PCB TechnologyMinimum Spacing
>6 layer board5 mils
2-6 layer board6 mils
Doubleside board8 mils
Thick copper boards>10 mils

Safety Margin

Adding margin prevents shorts from process variability:

  • 10-20% extra spacing for margin
  • More margin for prototyping vs production

Careful application of appropriate design rules ensures reliable trace isolation.

Trace Width Design Rules

Similar considerations guide trace width selection:

Based on Current

Wider traces allow higher current handling:

Trace CurrentMinimum Width
< 0.5A10mils
0.5A – 1A15mils
1A – 2A25mils
> 2A40mils+

May need further widening based on thermal rise limits.

Based on Impedance

Narrower traces yield higher impedance:

Target ImpedanceTrace Width
50 Ohms5-15 mils
75 Ohms6-25 mils
90-100 Ohms4-10 mils

Based on Manufacturability

Match trace width to fabrication capabilities:

PCB TechnologyMinimum Width
>6 layers4 mils
2-6 layers5 mils
Double sided8 mils

Many factors determine optimal trace widths for reliable performance.

Variable Width Traces

reducing the trace and space size
reducing the trace and space size

Varying trace widths along a net’s length can optimize performance:

  • Taper traces from wider at source to narrower at destination to minimize reflections.
  • Neck-down before sensitive pins to control impedance. Flare-out after pins.
  • Minimize stubs and branches by tapering off rather than abruptly ending.
  • Use wider traces only where needed for higher current. Narrow elsewhere.
  • Size for voltage drop along route – wider where drop is excessive.
  • Choke points at junctions intentionally narrow traces to control impedance.

Intelligently varying widths enhances SI performance while optimizing utilitization of available space on the PCB.

Example Trace Width Calculations

Here is an example procedure to calculate a suitable trace width:

Step 1. Determine Required Current

Check electrical schematics to identify the maximum continuous or pulsed current through the trace (Imax). Margin by 10-20%.

Step 2. Determine Maximum Supported Current Density

The PCB laminate material sets a maximum limit on allowable amps/unit cross section area:

  • Standard FR4 is 200 mA/mil2
  • High current FR4 rated for 300 mA/mil2
  • IMS substrates handle 500-1000 mA/mil2

Step 3. Calculate Minimum Trace Width

Use the max current (Imax) and max current density (J) to determine minimum trace width:

Trace Width (mils) = Imax (A) / J (mA/mil2)

Add margin of 20% for reliability. Round up to nearest 5 mils.

Step 4. Verify Against Other Design Rules

Increase width if required by voltage spacing rules. Reduce if other constraints require thinner trace (impedance, thermal relief around pads, etc). Iterate as needed.

With this approach, appropriate widths meeting both electrical and physical needs can be derived.

Example Trace Spacing Calculations

Similarly, trace spacing can be determined analytically:

Step 1. Identify Maximum Voltage

Determine the highest voltage that will be present between the traces. Include fault conditions and margin.

Step 2. Set Spacing For Voltage Clearance

Use table of spacing-to-voltage ratios to choose a spacing that prevents arcing.

Step 3. Evaluate Based on Other Needs

  • Adjust for target impedance needs if traces are controlled impedance.
  • Check crosstalk limits for high speed traces.
  • Verify against any manufacturing minimum spacing rules.

Step 4. Add Safety Margin

Increase spacing from calculations above by 20% as a safety factor for process variability.

Using a structured approach ensures trace spacing and widths chosen meet both electrical and fabrication requirements for a robust, reliable PCB layout.


  • Trace spacing and width selection directly impact layout density, electrical performance, manufacturability and cost.
  • Selection determined by current levels, voltage, target impedance, crosstalk, process capabilities, and safety margins.
  • Design rules guide spacing and width based on isolation, impedance, noise, fabrication limits, and reliability.
  • Sophisticated layouts taper traces, vary widths on net spans, and control junction impedances.
  • Analytic calculations combined with design rule checks validate trace geometries for optimal PCB performance.

Carefully choosing trace widths and spacings is a key PCB layout skill necessary to balance myriad electrical and physical design constraints.


How close can two traces be on a PCB?

The minimum spacing is set by voltage isolation needs and process capabilities. Traces under 50V can theoretically abut but at least 2x width spacing is recommended for margin. High voltage traces need much larger spacings.

How are trace widths measured?

Width is measured along the horizontal axis of the trace from soldermask edge to soldermask edge. The copper itself may be wider but spacing rules apply to mask-to-mask gaps.

Can track widths change on a single net?

Yes, tapering traces, widening only where needed, and impedance-controlling neck-downs allow optimization. However, abrupt changes in widths create impedance discontinuities and should be avoided.

What determines trace thickness on PCBs?

Copper thickness is generally fixed for a given PCB laminate and layer count. But wider traces inherently end up with more vertical copper thickness which aids current capacity through greater cross-sectional area.

How much spacing is needed between digital and analog traces?

A minimum of 3x-4x trace width separation is recommended, along with judicious use of ground planes. This prevents coupling noise from fast digital edges into sensitive analog nodes.

1. The signal circuit that needs to do impedance should be set strictly according to the circuit width and circuit spacing calculated by the pcb stack-up. For example, Radio frequency(RF) signal ( conventional 50R control), important single-ended 50R, differential 90R, differential 100R and other signal circuit, through the stack-up can calculate the specific circuit width circuit spacing (pictured below).

Stack up of Single Trace and Differential Trace Impedance Control

2. The circuit width and circuit spacing of the design should consider the production process capability of the selected PCB production factory. If the circuit width and circuit spacing are designed to exceed the process capability of the cooperating PCB manufacturer, it is light to add unnecessary production costs. It is serious that causes the design to fail to produce. Under normal circumstances, the circuit width is controlled to 6/6mil, and the via is 12mil (0.3mm). Basically, more than 80% of PCB manufacturers can produce it with the lowest cost.

The circuit width is controlled to a minimum of 4/4mil, and the via is 8mil (0.2mm). Basically, more than 70% of PCB manufacturers can produce it, but the price is slightly more expensive than the first case, not too expensive. The circuit width is controlled to a minimum of 3.5/3.5mil, and the via is 8mil (0.2mm). At this time, some PCB manufacturers can’t produce it, and the price will be more expensive. The circuit width is controlled to a minimum of 2/2mil, and the via is 4mil (0.1mm, which is usually a HDI blind buried hole design, which requires laser via).

At this time, most PCB manufacturers can’t produce the price, which is the most expensive. of. The circuit width circuit spacing here refers to the size between the circuit to the hole, the circuit to the circuit, the circuit to the pad, the circuit to the via, the hole to the pad and something like that.

3. Set the rules to consider the design bottlenecks in the design file. If there is a 1mm BGA chip, the pin depth is shallow, only one signal circuit needs to be taken between the two rows of pins, which can be set 6/6mil, the depth of the pin is deep, and two pins need to be taken between the two rows of pins. The signal line is set to 4/4mil; there is a 0.65mm BGA chip, which is generally set to 4/4mil;There is a 0.5mm BGA chip, the minimum circuit width must be set to 3.5/3.5mil; the 0.4mm BGA chip generally needs to be HDI design. Generally, for the design bottleneck,

the area rule can be set (for the setting method, see the end of the article [AD software setting ROOM, ALLEGRO software setting area rule]), the local circuit width is set to a small point, and the other rules of the PCB are set larger for production. Improve the PCB pass rate.

4. We need to be set according to the density of the PCB design, the density is small, the board is loose, the circuit width can be set larger, and vice versa. General can be set by the following steps:

1) 8/8 mil, 12 mil (0.3 mm) via.

2) 6/6mil,12mil(0.3mm)via。

3) 4/4 mil, 8 mil (0.2 mm) via.

4) 3.5/3.5 mil, 8 mil (0.2 mm) via.

5) 3.5/3.5 mil, 4 mil (0.1 mm, laser perforation) for via.

6) 2/2 mil, 4 mil (0.1 mm, laser perforation) for via.




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