HDI PCB Design: Escape Routing & Build Planning

HDI PCB design starts with access, not a layer-count label

HDI PCB design uses fine conductors and selected interconnect structures to connect a dense component field to the rest of the board. The useful question is not simply how many layers the board has. It is whether each signal can leave its pad, reach a suitable routing layer, retain a usable reference path and return to the intended destination within an agreed fabrication process.

Begin with the package footprint, pin assignment and electrical constraints. Then propose layer access, dielectric spans and via structures. Review that proposal with the fabricator before routing the complete board. This sequence helps prevent an attractive fanout from depending on an unavailable material thickness, an ambiguous laser-drill definition or an unsupported stack of interfaces. For ordering and construction review, use the HDI PCB manufacturing page; this guide focuses on the layout decisions that precede that discussion.

Separate the package problem into three routing tasks

The first task is local escape: getting from each solder land to a routing channel or via. The second is layer access: reaching the required plane or signal layer without consuming every channel with oversized lands. The third is global routing: completing the connection with appropriate impedance, return paths, coupling and length relationships. Passing one task does not prove the other two are feasible.

Classify the pins before choosing a fanout pattern. Power and ground connections may benefit from short, distributed connections to planes, while high-speed signals need suitable reference continuity and transition review. Pins marked unused still need the treatment required by the device documentation. Routing every ball with an identical pattern can waste the space needed by the few interfaces that determine the design.

Check a straight escape corridor

This worksheet compares a chosen number of traces with the space between equal circular pad projections. It includes a clearance at both outside edges and between neighboring traces. Enter conservative finished dimensions from the proposed construction. The output is a local width comparison; it does not infer total routing layers, select an IPC class or approve the complete footprint.

For an illustrative 0.50 mm pitch and 0.25 mm pad diameter, the straight corridor is 0.25 mm wide. Two 0.05 mm traces with 0.05 mm clearance require 2 × 0.05 + 3 × 0.05 = 0.25 mm. They fit exactly in this ideal model, leaving no additional width margin. Increasing the entered trace width to 0.06 mm makes the requirement 0.27 mm. That is a prompt to revisit the route, not to silently reduce the clearance.

Use a minimum pitch and maximum finished pad dimension when those bounds are available. If a process allowance has already been incorporated into the entered geometry, avoid counting it again. The calculator does not add registration, etch variation or manufacturing compensation behind the scenes. A downloaded brief preserves the inputs so the reviewer can see which assumptions produced the result.

Build a layer-access map before detailed routing

Draw the intended copper layers and mark the start and stop layer of every via family. Distinguish a laser opening into an adjacent dielectric from a mechanically drilled buried or through connection. A notation such as “L1 to L2 microvia” is much more useful than “small via” because it identifies the manufacturing span. Include the landing pad and any connection to another via on the next level.

Different fanout regions may require different structures. Outer rows might escape on the surface; deeper rows might need an additional signal layer. The plan should make these transitions visible rather than implying that every net must use the most complex via available. A simpler access pattern in one area may preserve routing space and reduce the population of demanding features elsewhere.

Keep the complete stack symmetrical where the chosen construction requires it, but do not mistake geometric symmetry for electrical performance. Reference-plane placement, dielectric thickness, copper distribution and manufacturing sequence all matter. Use the HDI stackup and sequential-lamination guide for the construction sequence; keep this page's corridor result as one input to that larger review.

Review the transition, not just the hole diameter

A microvia connects through a short dielectric span, but its capture geometry and target interface still need explicit requirements. Reducing its entry opening without revisiting target preparation or the land dimensions does not automatically produce a better design. When several microvias form a chain, the relationships between levels become part of the review. The PCB microvia guide separates those structures and provides an entry-and-target capture worksheet.

For a via inside a solder land, agree the completed surface that assembly will receive. Hole filling, metal capping and final finish are separate operations or requirements. A note saying only “fill vias” may leave unresolved whether solder can wick into an opening or whether the land meets the intended surface condition. Use the BGA via-in-pad review when the package interface drives that decision.

High-speed transitions also need a signal-integrity review. A short geometrical path is not necessarily a well-controlled impedance transition. Consider the nearby reference planes, clearances, return vias and discontinuities in the actual stack. Route through a deliberate reference change rather than relying on a final length-matching pass to repair the transition. The controlled-impedance planning tools support a different task from the local escape worksheet.

A practical sequence for a crowded controller board

Consider an illustrative controller with a dense processor package, several memory interfaces and connectors around the board edge. First identify the pins with the strictest routing and reference constraints. Reserve their escape directions and routing layers. Then map the power distribution and required return connections. Only after these areas are understood should the remaining low-speed signals consume the residual channels.

Suppose the initial fanout fits between pads but places a via land directly in a channel needed by another row. The corridor calculation did not fail; its scope ended before that obstruction. A useful revision might move the transition, change the assigned routing layer or use a different approved land arrangement. Record which physical conflict the revision solves. Avoid describing every change as “higher density,” because that obscures the tradeoff being made.

The same board may have a connector region that needs wider traces or larger holes. Maintain region-specific constraints rather than forcing the BGA's tightest geometry across the entire board. This makes the drawing easier to review and helps identify which features drive fabrication cost. It also gives the manufacturer a clearer basis for discussing an alternative construction.

Release files that explain the intended build

Keep the fabrication data, stackup drawing and via definitions on the same revision. For each drill family, state the layer pair, dimension convention and intended final condition. Identify selective fill populations explicitly; a reviewer should not have to infer them from the color of a CAD layer. Where a material or dielectric thickness is still provisional, label it as unresolved rather than presenting it as an approved production stack.

Ask the fabricator to distinguish process compensation from a change to the finished requirement. Adjusting artwork within an agreed process is different from changing the final trace width, pad size or dielectric thickness that the electrical design depends on. Document accepted alternatives and run the appropriate electrical and assembly checks again when those requirements change.

For quotation, send the board outline, quantities, complete stack proposal, via map and the constrained component regions. Add the relevant fabrication files and a concise list of open questions. The PCB DFM review can help organize that handoff. You can request review directly without completing any calculator.

Reduce unnecessary complexity before comparing prices

HDI cost depends on the proposed build, not only on the total layer count. Sequential processing, feature populations, material availability, panel utilization and required evidence can change the manufacturing effort. Compare quotations with the same layer access, fill requirements and acceptance scope; otherwise a lower number may describe a different board.

Useful design alternatives include fewer demanding transitions, a less restrictive local routing channel or a package orientation that simplifies access. Each alternative should preserve the electrical and mechanical requirements. Do not assume that deleting a build-up level is beneficial until the revised fanout and reference strategy have been reviewed. The HDI cost-driver guide explains the quotation inputs without presenting an unverified market price.

Questions engineers ask before committing to HDI

Use package and standards references in their proper scope

Texas Instruments' AM570x BGA escape-routing guide illustrates a package-specific routing approach. Its dimensions belong to that documented example; they are not generic RAYPCB design rules. The public IPC-2226A contents preview identifies HDI design topics, while the applicable licensed standard and agreed revision must be selected for the project. Neither reference turns the worksheet into a manufacturing approval.