Quick Presets

Layer Assignment (SIG-GND-SIG-PWR Pattern)
L1 SIG
L2 GND
L3 SIG
L4 PWR
L5 SIG
L6 GND
L7 PWR
L8 SIG
L9 GND
L10 SIG
L11 PWR
L12 SIG

Copper Layers (12)

Prepreg Layers (6)

Core Layers (5)

Total Board Thickness
2.000mm
2000 µm
vs 2.0mm
+0 µm
Copper (12L)
420 µm
Prepreg (6L)
826 µm
Core (5L)
800 µm

Stackup Visualization

L1 – Top SignalSIG 35µm
PP1 114µm
L2 – GND PlaneGND 35µm
Core 1 100µm
L3 – SignalSIG 35µm
PP2 114µm
L4 – PWR PlanePWR 35µm
Core 2 200µm
L5 – SignalSIG 35µm
PP3 185µm
L6 – GND PlaneGND 35µm
Core 3 (Center) 200µm
L7 – PWR PlanePWR 35µm
PP4 185µm
L8 – SignalSIG 35µm
Core 4 200µm
L9 – GND PlaneGND 35µm
PP5 114µm
L10 – SignalSIG 35µm
Core 5 100µm
L11 – PWR PlanePWR 35µm
PP6 114µm
L12 – Bottom SignalSIG 35µm
SOLDER MASK (BOTTOM)
Outer Signal
Inner Signal
GND Plane
PWR Plane
Prepreg
Core
💡 Common 12-Layer Targets
1.6mm: High-density HDI designs
2.0mm: Standard 12L (most common)
2.4mm: Server, networking
3.0-3.2mm: Backplanes, heavy copper
📐 Impedance Zones
Microstrip: L1→L2, L12→L11
Stripline: L3, L5, L8, L10
Broadside: L6↔L7 (tight coupling)
⚡ 12-Layer Design Strategy
6 Signal Layers: L1, L3, L5, L8, L10, L12 — Maximum routing density with 4 protected stripline layers.
3 GND Planes: L2, L6, L9 — Distributed ground reference minimizes return path inductance.
3 PWR Planes: L4, L7, L11 — Multiple power domains with L6-L7 forming a low-inductance decoupling pair.
Symmetry: Structure is symmetric about center for optimal warpage control during reflow.