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About Xilinx XC7K160T-2FBG484i of KINTEX-7

The Xilinx XC7K160T-2FBG484i is introduced in the Xilinx-7 FPGA series and the family consist of a total of 4 devices. First is the spartan-7 family that is famous for its low power, low cost, and best input/output performance. The devices of this family are available in packaging of smaller form factors for the management of the minor footprint of PCB. The second family is of Artix-7 that has a fame for its applications related to low power and requirement for serial transceivers, logical throughput, and better DSP slices. It yields a lower bill of materials maintaining higher throughput. The Kintex-7 family has double improvements when compared to its other families of devices yielding a novel FPGA class. The Virtex-7 is optimized for its exclusive system performance and double improvement in its system performance. This family is enabled with SSI technology.

The Xilinx XC7K160T-2FBG484i device bears detailed requirements of the system that ranges from little form factor, lower cost, sensitivity to costs, extreme high-end bandwidth connectivity, logical capacity, and capability of signal processing for demanding applications that require high performance of FPGA. This IC is manufactured on the grounds of advanced, lower power, higher performance, and 27nm high-k metal gate technology for enabling the unmatched performance of the system with its 2 million logical cells, 2.9 Tb per second of input/output bandwidth given that consuming 50 percent lesser power. The device also has to offer a completely programmable alternative for ASICs and ASSPs.

SSI Technology of Xilinx XC7K160T-2FBG484i

SSI stands for stacked silicon interconnect. Numerous challenges are connected with the creation of higher capacity enabled FPGAs that Xilinx is addressing through its SSI technology. This outstanding technology is enabling numerous superior logical regions to combine over a layer of passive interposer through the utilization of proven assembly and manufacturing methods for the creation of FPGA having thousands of interlinked SLRs delivering high connectivity of bandwidth with lower power consumption and lower latency. Two different SLRs are utilized in the Virtex-7 family i.e., intensive logical SLR and block RAM or DSP-based SLR. The technology is enabling a higher production capacity of Xilinx XC7K160T-2FBG484i FPGAs as compared to conventional methods of manufacturing.

Configurable Logic Unit

The architecture of the configurable logic unit comprises real six-input lookup tables. The lookup tables have distinct capability of memory storage along with shift register functionalities. The lookup tables of the Xilinx XC7K160T-2FBG484i devices can be either configured as a single six-input lookup table having a single output and 2 five-input lookup tables having distinct outputs but addresses are common and logic inputs too. Every output of the lookup table can also be registered in terms of flip-flops.

Clock Management

The clock management feature of the Xilinx XC7K160T-2FBG484i has several functions such as having high-speed buffers and low-skew clock distribution routing. The clock management also comprises phase shifting and frequency synthesis. This also has filtering of jitter and cock generation for lower jitter. Every device has approximately 24 of the clock management tiles out of which each has a clock manager for mixed-mode and single phase-lock loop too.

Mixed Mode Clock Management Features

The mixed-mode clock management is capable of having a fractional counter in any of its feedback paths that are also acting as a multiplier or it may have in one of its paths for output. The fractional counters are allowing increments of non-integer in 1/8 form resulting in an increment in frequency synthesis capacity through a factor of 8. This clock management is also delivering dynamic phase shifting for minor increments depending on the voltage-controlled oscillator’s frequency. The phase-shifting timer is incrementing at 11.2 ps per 1600 Mhz of frequency.

Clock Distribution

The Xilinx XC7K160T-2FBG484i FPGA is delivering 6 various kinds of clock lines for addressing the various types of requirements of clocking such as lower skew, small propagation delay, and higher fanout, etc. The clock lines are higher performance clock, BUFG, BUFMR, BUFR, BUFH, and BUFIO.

Global Clock Lines

Through the entire FPGA family of Xilinx XC7K160T-2FBG484i, 32 clock lines are having the highest fanout and are capable of reaching up to each flip-flop clock, reset/ser, logical inputs, and clock enable. A total of 12 global clock lines are there in every clock region that is driven through horizontal clock buffers. Every horizontal clock buffer is independently disabled/enabled which allows the clocks to be turned ON and OFF within a specific region, offering a fine control through clock regions that consume large power.

Regional Clocks

The regional clocks of Xilinx XC7K160T-2FBG484i are capable of running the clock destinations within its regions. The region is elaborated as an area that is 50 input/output, half chip wide, and 50 CLB wide. This family of FPGA is having 2 up to 24 regions. Every region is having 4 regional clock tracks. Every regional clock buffer can be driven from any 4 of the clock-capable pins at the input and its frequency can be divider through any integer in the range of 1 to 8.

Input / Output Clocks

The input/output clocks are very fast and are only dedicated to serving the input/output logics along with circuits of serializer and de-serializers. The device is having a dedicated connection starting from mixed-mode clock management to input/output for managing lower jitter and interfaces of higher performance.

Block RAM

The features of block ram of Xilinx XC7K160T-2FBG484i comprises of 36Kb dual-port RAM having the width of ports till 72. It has a programmable FIFO with integrated circuitry for error correction.

Synchronous Operation

Every of memory access write or rad is controllable through the clock. The entire write and read enable, clock enables, data addresses, data, and inputs are all registered. No function may occur without using a clock. The address of input is supposed to be clocked which enables data retention till the next operation. There is also an optional pipeline register for data allowing the highest clock rates given that an extra cycle of latency is provided. While write operation is in progress, data output is reflecting either in form of former saved data or novel was written data. This may also remain unchanged.