The Xilinx XC7K70T-2FBG484i belongs to the Xilinx-7 family of FPGA that comprises 4 categories of different FPGAs addressing a wide range of requirements for various systems that range from lower cost, the capability of signal processing, logical capacity, higher volume applications, cost sensitivity, and higher-bandwidth connectivity for demanding applications.
There are a lot of features of Xilinx XC7K70T-2FBG484i such as high-tech FPGA logic that is grounded over 6 of the inputs of lookup table that is configurable in the form of distributed memory as well. There is a 36Kb block RAM having an integrated FIFO logic for data buffering on the chip. With having support for DDR3 interfaces, the device has higher performance SELECTIO technology in a range of 1866 Mb/s. The serial connectivity of the device is high-speed enabled with an integrated multi-gigabit transmitter and receiver that range from 600Mb/s up to 28.06Gb/s. The transceiver is offering a dedicated lower power mode to have optimized chip-to-chip interfaces.
Xilinx XC7K70T-2FBG484i has an analog interface that is user-configurable and is incorporating a 12-bit analog to digital converter (ADC) along with thermal sensors on the chip. There are a couple of digital signal processing slices along with a 25×18 multiplier, pre-adder, and an accumulator of 48 bits for achieving the highest possible performance for filtering encompassing the optimized symmetric filtering. There is a powerful CMT module that combines the PLL and MMCM blocks for getting the lowest jitter and highest precision. There is a built-in block for the PCI Express for root port designs, and generation 3 endpoint. Furthermore, the device has support for a large range of configurations such as AES encryption of up to 256 bits along with SHA-256 or HMAC authentication and integrated SEU correction and detection.
Lookup Table, CLBs, and DSP Slices
There are some primary characteristics of the CLBs such as having a real lookup table with 6 inputs, a lookup table having the memory capability, and shift-register and register functioning. The lookup tables can be easily configured in the form of 64-bit ROM having single output or in the form of two 32-bit lookup tables each with 5 inputs and distinct output having shared logical inputs or addresses. Every lookup table is having the capability to be registered in the form of a flip-flop. A DSP slice is formed with the help of 4 lookup tables, 8 flip-flops along arithmetic carry logic and multiplexers. A CLB or configurable logic block is formed with the help of two DSP slices. Latches can be formed from the combination of any 4 of the 8 flip-flops per slice.
Clock Management of Xilinx XC7K70T-2FBG484i
The clock management architecture of Xilinx XC7K70T-2FBG484i comprises fast buffers and routing for lower skew distribution of clock along with phase shifting and frequency synthesis. The clock management block is also having jitter filtering and lower jitter clock generation. Every Xilinx XC7K70T-2FBG484i device is having 24 clock management tiles also referred to as CMT out of which each is consisting of a phase-lock loop and mixed-mode clock manager.
Mixed-Mode Clock Management Programmable Features
The mixed-mode clock management or MMCM is having a slight counter in any path used for feedback and is acting as a multiplier. The fractional counters are allowing the non-integer augmentations of around 1/8th ratio and are increasing the capabilities of frequency synthesis through a solid factor of 8. The MMCM is also capable of delivering dynamic or fixed phase shifts in minor increments that is depending on the frequency of the voltage-controlled oscillator or VCO. The increment of phase-shift timing is around 11.2ps at 1600MHz.
The key features of Xilinx XC7K70T-2FBG484i block RAM comprise of 36Kb dual-port RAM having the width of the ports up to 72. There is an integrated circuitry for error correction and a programmable FIFO logic. Each of the devices is having block RAM with dual-port around 5 to 1880. Every block of RAM is storing around 36Kb and every block of RAM is having two distinct ports that are storing the data only.
Every memory access, write or read is being controlled with help of a clock. The entire inputs, write and read enables, clock enables, data and addresses are registered. There is no function happening without a clock. The addresses of input are always clocked while having retention of the data till the next operation. There is a non-compulsory register for optional output data allowing the highest clock rates with an additional cycle for latency. While the write operation is in progress, the output data is reflecting previously stored data or the new data. However, the data may also remain unchanged.
FIFO Controller of Xilinx XC7K70T-2FBG484i
There is an integrated FIFO controller for synchronous or single clock and asynchronous or dual clock incremental operations for its internal addresses and is delivering 4 handshaking flags i.e., almost empty, empty, full, and almost full. Two flags are freely programmable i.e., almost empty and almost full. Like block RAM, the width of the FIFO controller along its depth is also programmable; however, read and write ports are having identical widths.
Output and Input Delays
Within the Xilinx XC7K70T-2FBG484i device, entire outputs and inputs could be configured in the form of registered or combinatorial. DDR is also having support for all of its outputs and inputs. Either of its outputs and inputs could be delayed individually with almost 32 increments of 39ps, 78ps, or 52ps. These delays are applied in the form of ODELAY or IDELAY. The delay steps could be set through configuration and could also be decremented or incremented while it remains in utilization.
Out of Band Signaling of Xilinx XC7K70T-2FBG484i
The receiver and transmitter of the Xilinx XC7K70T-2FBG484i are delivering the out-of-band signaling that is usually utilized for sending signals with lower speeds among transceivers. This is achieved whenever the link is in the power-DOWN phase.
Analog to Digital Converter
There are numerous features of the analog to digital converter of Xilinx XC7K70T-2FBG484i such as 1MSPS dual 12-bit ADC. The ADC is having the flexibility of up to 17 analog inputs that are user-configurable. There is an option for external reference as well. The temperature on-chip is having an error of ±4°C and its supply sensors are having an error of ±1%.