1. A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.


2. Single-ended and differential I/O standards with speeds of up to 1.25 Gb/s.


3. 240 DSP48E1 slices with up to 264 GMACs of signal processing.


4. Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.


5. Integrated block for PCI Express® (PCIe®), for up to x4 Gen2 Endpoint.


6. Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.


7. Low-cost wire-bond packaging, offering easy migration between family members in the same package, all packages available Pb-free.


8. Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology.


9. Strong automotive-specific third-party ecosystem with IP, development boards, and design services.


10. Some key features of the CLB architecture include:


11. Real 6-input look-up tables (LUTs) .


12. Memory capability within the LUT .


Register and shift register functionality The LUTs in 7 series FPGAs can be configured as either one 6-input LUT (64-bit ROMs) with one output, or as two 5-input LUTs (32-bit ROMs) with separate outputs but common addresses or logic inputs. Each LUT output can optionally be registered in a flip-flop. Four such LUTs and their eight flip-flops as well as multiplexers and arithmetic carry logic form a slice, and two slices form a configurable logic block (CLB). Four of the eight flip-flops per slice (one per LUT) can optionally be configured as latches. Between 25–50% of all slices can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32) or as two SRL16s. Modern synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features.