XA3SD1800A-4CSG484Q xilinx

XA3SD1800A-4CSG484Q

 

 

XA devices are available in both extended-temperature Q-Grade (–40°C to +125°C TJ) and I-Grade (–40°C to +100°C TJ) and are qualified to the industry recognized AEC-Q100 standard.

 

The XA Spartan-3A DSP family builds on the success of the earlier XA Spartan-3E and XA Spartan-3 FPGA families by adding hardened DSP MACs with pre-adders, significantly increasing the throughput and performance of this low-cost family. These XA Spartan-3A DSP family enhancements, combined with proven 90 nm process technology, deliver more functionality and bandwidth per dollar than ever before, setting the new standard in the programmable logic industry.

 

Because of their exceptionally low cost, XA Spartan-3A DSP FPGAs are ideally suited to a wide range of automotive electronics applications, including infotainment, driver information, and driver assistance modules.

 

The XA Spartan-3A DSP family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial mask set costs and lengthy development cycles, while also permitting design upgrades in the field with no hardware replacement necessary because of its inherent programmability, an impossibility with conventional ASICs and ASSPs with their inflexible architecture.

 

 

XA3SD1800A

 

 

XA Spartan-3a DSP FPGA Package Marking Example_XA3SD1800A-4CSG484Q

 

 

Key Features

 

1. 250 MHz DSP48A slices using XtremeDSP™ solution

 

2. Dedicated 18-bit by 18-bit multiplier

 

3. Available pipeline stages for enhanced performance of at least 250 MHz in the standard -4 speed grade

 

4. 48-bit accumulator for multiply-accumulate (MAC) operation

 

5. Integrated adder for complex multiply or multiply-add operation

 

6. Integrated 18-bit pre-adder

 

7. Optional cascaded Multiply or MAC

 

8. Dual-range VCCAUX supply simplifies 3.3V-only design

 

9. Suspend and Hibernate modes reduce system power

 

10. Multi-voltage, multi-standard SelectIO™ interface pins

 

11. Up to 519 I/O pins or 227 differential signal pairs

 

12. LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O

 

13. 3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling

 

14. Selectable output drive, up to 24 mA per pin

 

15. QUIETIO standard reduces I/O switching noise

 

16. Full 3.3V ± 10% compatibility and hot-swap compliance

 

17. 622+ Mb/s data transfer rate per differential I/O

 

18. LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with integrated differential termination resistors

 

19. Enhanced Double Data Rate (DDR) support

 

20. DDR/DDR2 SDRAM support up to 266 Mb/s

 

21. Fully compliant 32-bit, 33 MHz PCI® technology support

 

22. Abundant, flexible logic resources

 

23. Densities up to 53,712 logic cells, including optional shift register

 

24. Efficient wide multiplexers, wide logic

 

25. Fast look-ahead carry logic

 

26. IEEE 1149.1/1532 JTAG programming/debug port

 

27. Hierarchical SelectRAM™ memory architecture

 

28. Up to 2,268 Kbits of fast block RAM with byte write enables for processor applications

 

29. Up to 373 Kbits of efficient distributed RAM

 

30. Registered outputs on the block RAM with operation of at least 280 MHz in the standard -4 speed grade

 

31. Eight Digital Clock Managers (DCMs)

 

32. Clock skew elimination (delay locked loop)

 

33. Frequency synthesis, multiplication, division

 

34. High-resolution phase shifting

 

35. Wide frequency range (5 MHz to over 320 MHz)

 

36. Eight low-skew global clock networks, eight additional clocks per half device, plus abundant low-skew routing

 

37. Configuration interface to industry-standard PROMs

 

38. Low-cost, space-saving SPI serial Flash PROM

 

39. x8 or x8/x16 parallel NOR Flash PROM

 

40. Unique Device DNA identifier for design authentication

 

41. Complete Xilinx ISE® and WebPACK™ software support plus Spartan-3A DSP FPGA Starter Kit

 

42. MicroBlaze™ and PicoBlaze™ embedded processor cores

 

43. BGA packaging, Pb-free only