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QuickLogic PolarPro FPGA Family Introduction

When you think of technology, what’s the first thing that comes to mind? It could be smartphones and computers to drones, virtual reality systems, or even 3-D printers. Simply put, technology is all about working smarter and faster to accomplish more.

The rapid development of technology makes our world a much better place to live in. Moreover, technology improvement has helped solve some of mankind’s most challenging problems.

With the advancement of technology, today’s products are more varied and with many new features than ever before. From smartphones that can help you find your way around the city to home security systems that can alert you in an emergency, modern-day products make life simpler and easier.

However, even the most advanced devices can be difficult to use without proper knowledge and skills.

For instance, if you are out of the country and need to connect to the Internet, setting up your laptop for wireless Internet would be difficult. Furthermore, even if you have successfully connected to a Wi-Fi network, it would be tough for you to find helpful information on the Web without knowing how search engines work.

But thankfully, times have changed, and so has technology. These days there are plenty of small but powerful products specifically designed with the user in mind.

One of our favorite examples is QuickLogic’s PolarPro Family. This series of products is a complete suite of tools that includes a multimedia computer running on Windows OS and several mobile apps for iOS and Android.

QuickLogic PolarPro Family history

QuickLogic PolarPro Family is a collection of products created by QuickLogic, a CPU, graphics, and peripheral IC supplier based in China. Since the company started operations in 2005, it has expanded rapidly and caters to many different market segments worldwide.

QuickLogic PolarPro Family consists of three different products: PolarPro V1.0 for Windows; PolarPro V1.0 for iOS; and PolarPro V1.0 for Android.

The first version of PolarPro V1.0, released in June 2010, was the original Windows version. QuickLogic followed up with mobile apps for iOS and Android in December 2015.

QuickLogic PolarPro Family is suitable for both consumers and developers. While the former group can use it to engage in the media and perform other day-to-day tasks on their PCs or electronic devices, developers like Rayming PCB & Assembly can use it to build new applications.

Perhaps the PolarPro V1.0 for iOS and Android can be helpful to develop a new application that lets users quickly look up information on the Web. For example, an app could tell travelers their location and directions. In addition, one can develop apps that

But with so many options, how do you know which product is right for you?

QuickLogic PolarPro Family overview

QuickLogic PolarPro Family for Windows

The QuickLogic PolarPro V1.0 for Windows is a multimedia computer that can run all the popular applications on the market today. In addition, it is a full-featured operating system that has all of the latest technologies, such as 3D graphics, photo editing, and other functions.

PolarPro V1.0 for Windows can perform Internet searches, read e-books, play games, download videos, edit images and other content, listen to music and voice recordings, and much more.

PolarPro V1.0 for Windows enables you to work with all types of multimedia content in high-definition 4K or 1080p resolution via HDMI or DisplayPort connectors. You can also connect a TV through an S-Video or composite port to view videos on it.

PolarPro V1.0 for Windows can be helpful in nearly all scenarios, from home to business, and even in professional settings where you need to use a computer for tasks such as designing software or photo editing.

The PolarPro V1.0 for Windows has several useful applications to help you accomplish various tasks easily. For example, you can listen to music by using the built-in music player and Internet browser to access websites.

QuickLogic PolarPro Family for iOS

PolarPro V1.0 for iOS comes preinstalled on mobile devices, along with an app store that enables you to download more apps as per your requirements and preferences. This enables you to browse the Web, manage e-mails, keep a record of your expenses, play games, and perform other tasks efficiently with just a few taps on your mobile device.

QuickLogic PolarPro V1.0 for iOS also comes with a virtual keyboard feature that lets you type and send messages without worrying about typing errors. Instead, the keyboard works as per your requirements by predicting the next word in a sentence and auto-correcting any mistakes you make while typing.

PolarPro V1.0 for iOS can be helpful on Apple devices such as iPhones and iPads, but it is not limited to these devices alone. You can use it on other iOS compatible devices that run OS 6.0 or higher.

What makes PolarPro V1.0 for iOS stand out is the wide range of benefits that it offers and its efficiency and simple-to-use interface. For example, we can do app downloads quickly and easily.

PolarPro V1.0 for Android

The QuickLogic PolarPro V1.0 for Android is also a multimedia computer that runs on Android OS. In addition, the software package comes preloaded on mobile devices such as smartphones and tablets.

Like PolarPro V1.0 for Windows, the PolarPro V1.0 for Android can take full advantage of the latest technologies. In addition, it has a user-friendly interface that makes it easy to perform common tasks such as playing games, watching videos, and listening to music.

PolarPro V1.0 for Android has various applications that let you download multimedia content from the Internet in just a few taps.

These apps also enable you to communicate with friends and family by sending them e-mails or voice messages. You can also use some of these apps to read books and magazines through the built-in reader app or play games on your mobile device.

PolarPro V1.0 for Android is compatible with devices that run Android 2.3 or higher and support OpenGL ES 2.0.

Critical features for the QL1P1000-6PS324C QuickLogic PolarPro device

1. Process Data

The QuickLogic QL1P1000-6PS324C is fabricated on a 0.18µm process technology and delivers a 2D performance of 2.7 million square pixels/second, processing data at 7.2 Gpixel/s and drawing 260 million triangles/second.

To deliver the reference 256MB of frame buffer memory, the PolarPro device provides 1 Gbytes of internal memory on-chip and interfaces to system memory through 2×64-bit DDR3 channels running at 800 MHz or 64-bit SDRAM running at 400 MHz.

PolarPro depends on a 0. Six-layer metal CMOS process, ensuring the scalability and reliability of the chip.

2. Programmable Logic Architecture

The QL1P1000-6PS324C contains programmable logic modules that support the power requirements for all system components, including processors, memory, and peripheral components. It is a single register, the multiplexer-based logic cell containing several programmable logic blocks arranged in a technique that allows reprogramming the logic to meet the system requirements.

The programmable logic architecture allows flexibility in the design of systems. In addition, the programmable logic can be helpful to offload specific tasks from processors, such as image processing, audio and graphics processing, scheduling, and some communications processing.

You will find high fan-in per component and high fan-out per package in our devices. The high fan-in per component is due to the flexible nature of the architecture and the flexible routing of interconnects.

3. RAM Modules

The PolarPro QL1P1000-6PS324C contains five DIMM slots and a single slot for memory cards. It draws power from the CPU through a multi-phase design that handles the voltage and current delivery to the RAM modules.

Each DIMM can handle two 64-bit DDR3 modules, accessing them through 72-pin SODIMM sockets.

The devices also provide redundancy by using redundant sockets, which allow data transfer to be interrupted by request while it is transferring data. Its features include:

a) Non-pipelined read data path: The PolarPro device can use all memory bandwidth even when using only a single module. This feature is also available in the clock domain.

b) Write byte enables: The CPU can write data directly from the buffer and use it as input for further computations. This feature also provides read-while-write support.

c) Vertical and horizontal concatenation: The device can combine vertical and horizontal data blocks into one transaction.

d) Independent read and write clocks: The device uses independent clock domains for read-data and write-data, respectively.

e)  Independently configurable r/w data bus widths: The read and write clock can be independently configured.

4. True Dual-Port RAM

In addition to its five single-ended RAM modules, the device also provides an actual dual-port RAM that supports two independent clocks, allowing additional processing. We implement the dual ports in the following:

a) Block data transfer from memory to memory: The RAM blocks may split into different sections for transfer between the two modules.

b) Multiplexed read and write accesses: Multiple reads and writes can occur simultaneously across all modules of the device. For example, it is possible to write to one memory section while reading from another memory location.

c) Single-cycle read and write access: The device performs a read or writes at a single cycle of the clock input. This feature allows various operating modes with reduced latency and power consumption.

d) Data transfer between two RAM modules: The device can access two distinct data sections in two separate RAM modules within the same clock edge. This feature allows DMA transfers with reduced latency and power consumption.

It is important to note that no circuitry prevents a write and read operation from happening simultaneously. So, this feature is true to the point that there is no memory access violation.

The physical architecture of the QL1P1000-6PS324C requires additional power to supply all the components. It includes a 200 MHz clock for all RAM modules, a 200 MHz clock for each dual-port RAM module, and a 100 MHz clock for the CPU.

5. Embedded FIFO Controllers

The PolarPro device contains embedded FIFO controllers used in sending and receiving data. The embedded FIFO controllers support the following features on the QL1P1000-6PS324C:

a) Different types of stream control: The FIFO controllers support different streams such as control registers and video processing.

b) In-order double-buffering: The device has two banks to handle updates to two different devices. This allows continuous data communication with reduced latency.

c)  Pipelined read data to improve timing: The devices have a two-stage pipeline that provides data at the output of the first stage and input to the second stage simultaneously. This reduces latency as well as power consumption.

d) Independent read and write clocks: The device uses independent clock domains for read-data and write-data, respectively, for each FIFO controller. These registers allow data synchronization in non-critical paths separately from critical paths to reduce latency.

e) 4-bit PUSH and POP level indicators: The push and pop FIFO registers have a 4-bit level indicator that shows the number of data bytes written to or read from the FIFO.

f) Configurable FIFO operation: The device is essential for synchronous or asynchronous operation for each FIFO. The synchronous and asynchronous modes have an independent write clock domain, read bus width, and bit-width.

g) Independent programmable data: The device supports independently programmable widths for all bytes pushed into the registers, and all bytes popped out of the register.

6. FIFO Flush Procedure

Both PUSH and POP domains come with dual-port RAMs. All data written to the FIFO controller is stored in a RAM when written into one port and then read out through the other port. The two ports connect using a single transfer bus, and this bus operates in two modes:

a) Transfer mode: In the transfer mode, data may move between two FIFO registers or between a FIFO register and memory. We treat two registers as one single 32-bit buffer in the transfer mode.

b) Read mode: Data from a single FIFO appears through a single port stored in RAM.

The flush procedure allows the devices to execute these functions without blocking other devices with minimal interference. It also supports simultaneous flushing of all FIFO domains to reduce latency and remove errors.

The DC input to all RAMs turns on when a flush is triggered and executes a flush cycle. The DC input to the FIFO controller is turned off at this point to avoid turning it on before the device has finished reading data from one of its ports. After an entire bus cycle has elapsed, the devices initiate an additional bus operation that puts all the RAMs back into their normal states.

7. Clock Network Architecture

To achieve its high performance, the device contains a clock network architecture designed to eliminate bugs in clock domains and reduce interference. A global unsynchronized differential clock operates at 200 MHz. All critical functions of the device depend on this clock. The global clock has six independent clocks at 100 MHz each, and they are distributed selectively to essential components of the devices.

Distributed Clock Networks:

It consists of a 3-level H-tree network. All six of the devices contain one H-tree network. The H-tree network has two clocks: primary and secondary clocks. The primary clock is helpful for critical operations, such as power and system initialization, configuration, RAM initialization, and debugging operations. The secondary clock is helpful for subcritical, such as interrupts, serial ports, and on-chip timers.

Dynamic Clock Enable:

Each clock network can automatically disable itself when not needed. When a network is disabled, the secondary clock in each node is also disabled. This feature allows the device to sleep and wake up quickly. This capability is used on each node to identify critical and non-critical nodes. For example, the power and system initialization domain are essential, while other domains are considered non-critical. Therefore, the power and system initialization domain will be enabled only when an external reset source drives the device into its active mode.

Configurable Clock Managers (CCMs):

The devices contain four 16-bit single-cycle CCMs used by the CPU to handle signals in each clock network. The CCMs vary the speed and phase of their clocks according to the incoming signals. For example, the input frequency could range from 10-150MHz. The output frequency could range from the input frequency to half of the input frequency. The conversion ratio is (1/2)n, where n = number of stages in the CM. The domain that controls the maximum frequency determines whether it is a critical or non-critical domain.

Simultaneously Switching Outputs:

The devices allow SSO and CM to work simultaneously. Since the SSOs require a longer time than a single cycle, the clocks with higher frequency may use the same output of a CCM. The nodes are capable of utilizing this capability to reduce DC power consumption. As shown in figure 1 above, six independent clocks operate in each device. These clock domains include:

i) VDEDAC: This domain provides the timing signals to control the operation of VDEDAC circuits on each pixel engine. It receives signals from the SCM and collation circuits. In addition, the VDEDAC circuit is responsible for delivering clocks to a few pixel engines.

ii) Clock Controller: The clock controller controls each clock’s timing, frequency, and phase. It can switch between CCMs and their outputs or SSOs at any time without losing synchronization with VDEDAC and SCM. The clock controller monitors all the 16-bit single-cycle CCMs and, if needed, enables them to operate simultaneously. The following signals monitor the VDEDAC and SCM:

1) SDCB: We use this signal by the SCM to synchronize with VDEDAC.

2) SYNCB: SYNCB is a signal provided by the CAMP. The SCM uses this signal to implement synchronous operation with VDEDAC within a certain time scale.

8. GPIO Cell Structure

There are three main functional blocks in a GPIO cell: data latch, flip-flop, and output driver. The data latch is helpful to store data during transfer and check the data’s status. This block also receives signals from the SCM VDEDAC and outputs CCM current. We use the flip-flop to generate output control signals. It also receives input control signals from the CCM, SDCB, and SYNCB. Finally, the output driver controls current levels and output timing to meet each port’s data transfer requirements. It also receives data from the data latch and supplies current to the load drivers according to the data from the flip-flop.

With global clock input pins and bi-directional I/O pins, this block can be helpful as a functional block and a communication interface. Each GPIO cell has three outputs and one input. The outputs are used for the data transfer and global clock input, while the input is essential for the data transfer from the host system and global clock output.

9. DDRIO Cell Structure

It allows clocking data on the negative and positive clock edges. The DDRIO adaptor block includes a finite state machine and a flip-flop. The flip-flop stores data to control output signals. There is one output for each port of the device. Depending on whether the port needs to transfer data, the corresponding outputs will be disabled or enabled using the input/output control signals from CCM. You can configure the I/O using the configuration mentioned earlier tools.

10. Very Low Power Mode

It is a mode to reduce power consumption beyond the device’s dynamic power reduction mechanisms (clock gating, power, system initialization domains, etc.). In this mode, application modules in the device turn off when they do not need using at a particular time. It reduces power consumption by about 30 percent compared with non-sleep mode. In addition, they can bring the standby current to below 10 µA.

The main advantages of employing FPGA are customization, low power consumption, and flexible circuit layout. But like most other methods of IC design, the FPGA technology is not perfect, as it involves higher costs and lower performances compared with digital circuit design at a certain level of integration. In addition to that, each time an FPGA needs to be modified or debugged, it must burn. Quickly building the hardware circuit is one of the advantages of FPGA technology. But once you have built your design, it will be challenging to change it. After the burn-in test, you can only modify the existing hardware circuit layout or add new functions to your hardware circuit.

11. Joint Test Access Group (JTAG) Information

JTAG signals are not common to all FPGAs. To ensure the correct operation of the QL1P1000-6PS324C devices, you must use JTAG signals for testing and debugging purposes. The JTAG connector is located under the circuit board and can connect with a JTAG debug board (JDR-4X4 or similar type). There are two types of pins: negative test pins and positive test pins, each helping the corresponding PCB side. QL1P1000-6PS324C devices operate in the following test modes: soft reset and hard reset.

The QL1P1000-6PS324C devices have a serial debug port (SPORT) that can help conduct device mode-independent debugging. The SPORT is attached to the JTAG port of the QL1P1000-6PS324C PCB.

a)  Bypass Instruction: The host computer can access all the device’s resources in bypass instruction mode. All packages are accessible except for those locked into lower power consumption states. This mode is helpful to check the device’s operation, monitor signals, and check variables’ values.

b)  Sample/Preload Instruction: This helps access the device’s memory space. The target addresses of data, control, and address bytes move via a JTAG (serial) link to the QL1P1000-6PS324C device.

c)  Extent Instruction: This helps access the device’s internal logic. If a fault occurs during the test procedure, the device will send an error code to the host computer. This mode can debug your design when you are using JTAG signals.

12. Electrical Specifications

In order to provide its users with the best performance and highest reliability, the QL1P1000-6PS324C device has the following specifications:

1) VDEDAC :

a) Input Voltage: +5 Vpp to +15 Vpp

b) Output Voltage: 0.8 Vpp to 2.4 Vpp

c) Operating Temperature: – 40 °C to +85 °C (±0.5°C)

d) Package Type: QFP-80P

2) CCMO :

a) Output Voltage: 0.8 Vpp to 2.4 Vpp

b) Operating Temperature: – 40 °C to +85 °C (±0.5°C)

c) Package Type: SOT-23-3

3) RPU :

a) Output Voltage: 0.8 Vpp to 2.4 Vpp

b) Operating Temperature: – 40 °C to +85 °C (±0.5°C)

c) Package Type: SOT-23-3

4) PLL :

a) Operating Voltage: 4.75 Vpp to 5.25 Vpp

b) Frequency Range: 790 MHz; 800 MHz; 860 MHz; 900 MHz; 950 MHz; 1000 MHz.

Conclusion

 In conclusion, the PolarPro Devices QL1P1000-6PS324C provides a wide range of memory and FIFO-related functions that can help develop complex applications. The device is specifically suitable for video processing and graphics applications that require high data bandwidth. The PolarPro QL1P1000-6PS324C RAMs are ideal for any application that requires fast access to high-performance data.