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Xilinx XC7Z015-2CLG485i Zynq 7020 FPGA

The Xilinx XC7Z015-2CLG485i is grounded on the architecture of Xilinx SoC. This device is integrating a single or dual-core ARM Cortex central processing unit with 28 nm programmable logic. The ARM Cortex is considered as its heart and has included on-chip memory, rich interfaces for peripheral connectivity, and external memory interfaces too.

Features of Xilinx XC7Z015-2CLG485i

The application processor unit of the device has 2.5 DMIPS per MHz per central processing unit and the frequency of its CPU is up to 1 GHz. With its coherent multiprocessor support, single global timer, couple of triple timer counters, interrupts, and timer, the processing system of Xilinx XC7Z015-2CLG485i is outstanding. The cache of the device has byte-parity support, 8-way set associative level 2 cache of 512KB, and 4-way data caches of level 1 with 32KB capacity. The device has on-chip bootable ROM along with on-chip RAM of 256KB and support for byte-parity. Numerous interfaces of the device can be used such as 16 or 32-bit interfaces for LPDDR2, DDR2, DDR3L, and DDR3 memories, 16-bit support for ECC, address space of 1GB through 8, 16, or 32-bit memories, interface for static memory, and 1, 2, 4, or 8-bit serial NOR flash. There is a DMA controller of 8 channels scatter-gather transaction, peripheral-to-memory, memory-to-peripheral, and memory-to-memory support.

Various input/output interfaces and peripherals are available in the device such as 2 tri-speed ethernet peripherals having an IEEE standard protocol of 802.3 and 1588 support. There are two USB 2.0 peripherals with support of up to 12 endpoints. Higher bandwidth connection in between PL and PS and within PS is possible. The device has lookup tables, adders in cascaded mode, and flip-flops along true dual-port 36KB blocked RAM working up to 73 bits, and configurable 18KB blocked RAM. The DSP blocks of the device have a pre-adder of 25-bit and an accumulator of 48-bit. JTAG of the IC is of IEEE 1149.1 standard. It supports 8 lanes, Gen2 speeds, endpoints, and root complex configurations. The IC has 16 transmitters and receivers.

Family Description of Xilinx XC7Z015-2CLG485i

The Xilinx XC7Z015-2CLG485i offers both scalability and flexibility along with outstanding performance, low power consumption, and easy utilization, especially with ASSP and ASIC. The designers of the device are targeting high performance and cost-effectiveness using a single platform through the utilization of tools of industry standard. The device can serve a vast range of applications such as infotainment, driver information, and driver assistance in the automotive industry. Other applications comprising of the broadcast camera, machine vision, industrial networking, motor control, smart camera, LTE radio, imaging, and medical diagnostic, printers, night vision, and video capturing equipment.

The architecture of Xilinx XC7Z015-2CLG485i is enabling custom logic implementation in PL along with customized software in PS. It is also allowing the realization of differentiated and distinct functions of the system. The PS and PL integration is allowing higher performance levels that ordinary two-chip solutions are not able to match because of their limited input/output power budgets, latency, and bandwidth. The application processor inclusion is enabling a higher level of operation of the system.  Both PL and PS have separate power domains allowing the users for powering down PL if required. The PS processors are always booting first which allows a software-centric approach for PL configuration.

Dynamic Memory Interfaces

The DDR memory controller that is multi-protocol enabled is configured to deliver 16 or 32-bit access to its 1GB address space through the use of a single configuration of 8, 16, or 32-bit DRAM memories. While ECC has the support of 16-bit mode, PS is incorporating DDR controller and its PHY comprising of its dedicated input/outputs. The DDR3 is supporting a speed of up to 1333 megabits per second. the multi-port nature of memory controller DDR is enabling the system’s processing and programmable logic for having common memory and shared access. DDR is having 4 AXI slave ports for this purpose. One of the 64-bit ports is devoted to the central processing unit through its L2 cache controller that is configurable for lower latency. Furthermore, two 64-bit ports are also devoted for PL access and 1 of the 64-bit port is for AXI masters through a central interconnect.

Static Memory Interfaces

The static memory interfaces of Xilinx XC7Z015-2CLG485i are supporting external static memories with 8-bit of SRAM data for support up to 64MB, 8-bit parallel NOR flash for support up to 64MB, and 1-bit ECC for support of NAND flash.

Interconnect

The IOP, APU, and memory interface unit of Xilinx XC7Z015-2CLG485i are interconnected to PL via multi-layered interconnected ARM AMBA AXI. This interconnect is non-blocking in nature and is supporting numerous of master-slave transactions. The interconnect is designed in such a manner that it has a sensitivity for latency so as ARM CPU has the shortest path for its memory and its bandwidth is also in the master state. This illustrates that PL master has higher throughput connectivity with its slaves for communication. The traffic via interconnect is being regulated via quality of service block through interconnect. Furthermore, the quality of service feature is utilized for regulation of generated traffic through DMA controller and CPU along with combined entity for representing master through IOP.

Programmable Logic

The programmable logic of the Xilinx XC7Z015-2CLG485i is comprising of a CLB, 8 lookup tables in each CLB for distributed memory or randomized logic implementation. The memory lookup tables are also configurable in the form of 32×2 or 64×1 bit or in the form of shift registers. There are 16 flip-flops in each CLB. Two 4-bit adders are there for arithmetic functions that can be cascaded. There is a block RAM of 36KB. The DSP slices of the Xilinx XC7Z015-2CLG485i are 18×25 multipliable. There is an adder of 48-bit. The input/output blocks are programmable. Support is available for common input/output standards encompassing SSTL, LVDS, and LVCMOS. There is a built-in programmable input/output delay. There is an option for selecting lower power consuming serial transceivers. There is an integrated root port/endpoint block for PCI express in few versions of Xilinx XC7Z015-2CLG485i. There are two analog-to-digital converters of 12-bit. There are sensors available on-chip for temperature and voltage control. There are 17 external input channels of differential mode and a configuration module for PL.