The Xilinx XC7Z015-1CLG485C device belongs to the Zynq-7000 series family and is grounded on the top-notch SoC architecture offered by Xilinx. These devices are integrating a single dual-core ARM Cortex A-9 state-of-the-art processor which is feature-rich. Moreover, these devices have outstanding processing systems based on 28nm programmable logic. The CPUs of the devices are considered processing system’s heart and are having memory integrated on-chip, interfaces for external memory, and interfaces for peripheral connectivity as well.
There are abundant features of the processing system of Xilinx XC7Z015-1CLG485C such as 2.5 DMIPS per MHz per central processing unit, the frequency of CPU can range up to 1GHz with support for coherent multi-processor. The architecture of the processing unit is based on ARMv7-A, security is of TrustZone along with instruction set of thumb-2. The environment of RCT execution is offered by Jazelle with the engine for media processing by NEON. The processing unit has interrupts and timers, 3 watchdog timers, a global timer, and 2 counters for the triple timer. The cache of the device has support for byte parity, eight-way 512Kb set-associative cache of level-2, and four-way 32Kb set-associative level-1 data caches and instruction. There is a boot ROM on-chip, support for byte-parity, and RAM of 256Kb on-chip. Xilinx XC7Z015-1CLG485C has a multi-protocol memory controller for dynamic purposes, 16 or 32-bit interfaces for its DDR memories, and a 16-bit support mode for ECC. The device has an interface for static memory, support for NOR flash, address space of 1GB through the utilization of 32, 16, or 8-bit memories, and an 8-bit data bus for SRAM supporting up to 64MB.
The zynq-7000 series FPGA family is best suited for high bandwidth connectivity within PS and among PL and PS and has the support of QoS for critical matters for control of bandwidth and latency. The configurable logic blocks or CLBs of Xilinx XC7Z015-1CLG485C have lookup tables, adders cascaded together, and flip-flops. The block RAM of 32Kb is dual-port, supports up to 72 bits, and can also be configured as two parts in 18Kb. The DSP blocks have a pre-adder of 25-bit, an accumulator or adder of 48-bit, and a multiplier of 18×25. The PCI express of the device has support for endpoint configurations and root complex. It also has support for Gen2 speeds and 8 lanes. The transceivers are in serial mode and have about 16 transmitters and receivers with support up to data rates of 12.5Gb/s. There are a couple of 12-bit ADC or analog to digital converters having support for temperature and voltage sensing, have around 17 external input channels, and a conversion rate of up to one million samples every second.
The processor system of Xilinx XC7Z015-1CLG485C contains four main blocks i.e., interconnects, peripherals for inputs/outputs, an application processing unit, and interfaces for memory.
Interfaces for Dynamic Memory
The controller of DDR memory which is multi-protocol could be configured for delivering 16 or 320bit accesses to the 1Gb address space through the utilization of unity rank configurations of 32, 16, or 8-bit DRAM memories.16-bit busses are utilized for support of ECC with the mode of bus access. PS is responsible for the incorporation of associated PHY and controller for DDR, comprising of its own input/output. The speed of the device could range to 1333Mb/s for its DDR3. The memory controllers of DDR memory are multi-port, capable of enabling the programmable logic and processing system for common access for shared memory and the controller of DDR is featuring 4 AXI ports in slave mode for the purpose.
Interfaces for Static Memory
The interfaces of the Xilinx XC7Z015-1CLG485C for static memory have support for static memories. The 8-bit data bus of SRAM is having the support of 64MB, 8-bit NOR flash is having the support of 64MB, and 1, 2, 4-bit SPI or a couple of quad-SPI serial NOR flash.
Accelerator Coherency Port
The ACP or accelerator coherency port of Xilinx XC7Z015-1CLG485C is 64-bit and has an interface of AXI slave providing connectivity among potential accelerator function and APU in PL. The ACP is connecting the PL and snoot control unit directly for the ARM Cortex A-9 processor that enables access for cache-coherence for the central processing unit’s data through both caches L1 and L2. ACP is also delivering a lower latency path among the PL and PS grounded accelerator whenever compared along with the legacy cache loading and flushing scheme.
The Programmable Logic of Xilinx XC7Z015-1CLG485C
The key features of the programmable logic of the device comprise configurable logic blocks or CLB and 8 lookup tables within every CLB for distributed memory or random logic implementation. The lookup tables are configurable in either one of 64-bit or two of 32-bit RAM. The lookup tables can also be configured as a shift register. There are 16 flip-flops in every CLB, a couple of 4-bit cascaded adders, block RAM of 36Kb that is 36-bit wide.
The outputs of Xilinx XC7Z015-1CLG485C that are single-ended are utilizing a traditional CMOS pull/push output structure that is driving it to a high state whenever towards VCCO and is driving it low whenever towards GND. The single-ended outputs can also be put to a z-state. The designer of the system is capable of specifying output strength and slew rate. The input is to be in an active state forever; however, it is often ignored whenever the output is in an active state. Every pin of the device may have an optional weak pull-down or pull-up resistor. Most pairs of signal pins can be terminated along with a 100 Ohms resistor.
System-Level Functions of Xilinx XC7Z015-1CLG485C
Various functions are spanning both PL and PS comprising reset management, device configuration, power management, clock management, along with support for software and hardware debugging.
The primary function of reset management is delivering the capability for the device to reset the device or even certain individual units within the device. The PS is having support for the signals and reset functions such as warm reset, reset for security violations or locked down reset, PL user resets, internal and external power-ON signal reset, reset for a watchdog timer, and resets for JTAG and software.