The Intel Agilex series marks the latest generation of FPGAs from Intel, succeeding the Stratix 10 lineup. First released in 2019, Agilex combines innovations in underlying FPGA fabric along with advanced SoC architecture to address the growing needs of data-centric applications.
This article provides a technical deep dive into the Agilex FPGA family. We examine the new HyperFlex architecture, embedded memory and DSP blocks, transceiver innovations, integrated PCIe 5.0, security features, device family variants and target applications for Agilex FPGAs.
Intel Agilex FPGA Overview
Here are some key highlights of the Agilex generation of Intel FPGAs:
- Manufactured on 10nm process with 2nd generation HyperFlex architecture
- Densities up to 1.7M logic elements (LE), 90Mb RAM and 48Mb FIFO
- Up to 112G transceivers, PCIe Gen5 Hard IP blocks
- Embedded controllers based on dual ARM Cortex-A53
- Advanced security framework with cryptography accelerators
- Support for HBM2/HBM2E memory integration
- Designed for Data Center, Networking, Wireless Infrastructure and Military applications
HyperFlex FPGA Architecture
Agilex FPGAs leverage an innovative fabric architecture called HyperFlex to deliver customized flexibility and performance.
The basic building block of HyperFlex architecture is called a HyperTile. Each HyperTile contains:
- Programmable Logic Blocks for implementation of logic
- Local Hyper-Registers for sequential elements
- Embedded Memory Blocks
- DSP Slices for arithmetic operations
- Interconnect for routing
By repeatable tiling of HyperTiles, different variants can be created within a single device family like Agilex.
A key capability of HyperFlex architecture is its adaptability to application requirements through the mix of HyperTile types, interconnect bandwidth and Precision DSP blocks.
HyperFlex enhancements yield significant gains over previous generation FPGAs:
- Up to 40% higher logic density
- Up to 2X increase in DSP performance
- Up to 40% power savings
Combine to make Agilex suitable for high performance computing applications.
Agilex Device Family
The Agilex portfolio offers variants optimized for different application needs:
|Agilex F||Optimized for lower cost and power|
|Agilex I||High bandwidth I/O|
|Agilex M||High DSP and memory density|
Density options scale from 100K to 1.7M LEs. Higher density M models will be added in future.
Embedded Memory Blocks
On-chip memory resources available in Agilex FPGAs include:
M20K – 20 Kb embedded memory blocks, up to 3,522 blocks per device
MLAB – Smaller 640 bit registers, up to 1,966 per device
Provide 90Mb of embedded RAM along with advanced ECC support.
Integrated DSP Blocks
Agilex FPGAs integrate high performance DSP blocks called Hyper-DSP slices. Each slice contains:
-Multiply adder unit with 27×27 multiplier
Deliver up to 7.4 TeraMACs of signal processing capability for wireless and image processing applications.
Analog mixed signal capabilities are enabled through:
FPAAs – Field Programmable Analog Arrays integrate programmable analog blocks
DSPs – Allow implementing data converters and PLLs
RTLs – Routable clock networks for synthesizing converters
PCI Express Hard IP
To support high speed interconnect, Agilex offers hardened PCIe Gen5 controller blocks with up to 32 lanes at 32GT/s data rates.
Delivers over 256GB/s bandwidth for 5G, networking and compute acceleration workloads.
Integrated HBM Memory Controllers
Large memory bandwidth is enabled by supporting integration of High Bandwidth Memory (HBM):
- HBM2 – Up to 8-Hi stacks, 2.4Gbps per pin
- HBM2E – Increased to 3.2Gbps per pin speed
Provides bandwidth up to 410GB/s from a single HBM2E stack.
Embedded ARM Controllers
Dual core ARM Cortex-A53 processors running up to 1.5 GHz are available as hard controller blocks. Used for managing and monitoring the FPGA fabric.
To safeguard applications, Agilex includes:
- Hardware Root of Trust for secure device identity
- DPA countermeasures and side channel analysis mitigation
- AES-GCM 256-bit cryptography accelerators
- Tamper resistant design with sensitivity analysis countermeasures
- Support for securely downloading and updating FPGA images in the field
SerDes connectivity up to 112G PAM4 is enabled through enhancements like:
Multirate support – Ability to individually configure each lane’s rate from 6.4Gbps to 58Gbps
DSP Engine – Programmable DSP in each transceiver for defining equalization, sorting and interleaving
Embedded eye monitors – Monitor link health, eye diagrams without external equipment
Soft CDR – Digitally configurable clock data recovery allowing rate matching
Design and Programming
Agilex FPGAs are programmed using:
OpenCL – High level programming framework to accelerate applications in hardware.
Agilex families address a diverse set of workloads:
Data Center – Network acceleration, AI inferencing, big data analytics, storage
Wired Networking – 100G to 400G packet processing, network attached storage
Wireless 5G – Base stations, backhaul infrastructure, Remote Radio Heads (RRH)
Military/Avionics – Radar, communications, image processing
Test and Measurement – High speed automated test equipment (ATE)
Broadcast – Video bridging, compression, graphics
Frequently Asked Questions
What is the main innovation in Agilex architecture?
Agilex employs the new HyperFlex architecture which provides customizable FPGA fabric using tiles with adaptable interconnects, memory and DSP blocks. This architecture can be optimized across variants for specific application needs.
How does Agilex compare against earlier Intel FPGAs?
Agilex delivers higher performance, density and bandwidth compared to previous generation Stratix 10 FPGAs based on a 10nm manufacturing process and architectural enhancements.
What are the key application areas for Agilex FPGAs?
The primary segments for Agilex are Data Centers, Wired and Wireless Network Infrastructure, 5G, Military Embedded Systems, Test and Measurement Systems and Broadcast Video.
What is the main benefit of embedded controllers in Agilex?
The integrated ARM Cortex-A53 controllers allow managing the FPGA fabric, system bring up, communicating with host processors and implementing control logic without consuming programmable logic.
How does Agilex enable integration of HBM memory?
Agilex provides HBM2 and HBM2E memory controllers as hard IP blocks, enabling large external HBM stacks to be interfaced over high speed channels delivering up to 410GB/s bandwidth.