An FPGA is a type of integrated circuit used in communications applications to perform various tasks. These tasks include the LOW-PHY function, data transfer, synchronization between the device and host memory, support for multiple air interfaces, and a high-performance RF transceiver portfolio. This article will discuss the LOW-PHY function in FPGAs and some of their other benefits.
LOW-PHY function in FPGA
The LOW-PHY function in FPGA can be used in 5G networks and is an essential component of the RF subsystem. We can efficiently implement the Low-PHY function in FPGA, resulting in lower power consumption, greater resource utilization, and faster data transfer speeds. It is currently implemented on the CPU and can operate at frequencies ranging from 0.5GHz to 1.2GHz.
In FPGA 5G, the LOW-PHY function is crucial to improve signal quality. The Low-PHY function implements the IFFT process, which converts IQ samples from the frequency domain into the time domain. In addition, it inserts a cyclic prefix (CP) to avoid inter-symbol interference. We then perform the IFFT operation on the samples in the time domain for the downlink and uplink directions.
Low-PHY implementations in FPGAs require at least 2048 IFFT points, but we can scale them to higher numbers. Furthermore, the proposed solution reduces the processing time by implementing auto-run kernels and parallelizing the Low-PHY function. In addition, this solution depends on I/O OpenCL channels. This means that the Low-PHY function can operate independently of global memory.
Data transfer and synchronization between the host and the device memory
Current solutions do not easily solve the challenges of time synchronization and data transfer between the host and device memories of an FPGA. The multi-cloud and distributed nature of cloud-native RAN deployments make them inefficient. Existing FPGA-based vRAN solutions are unable to meet these demands.
The system includes systems and methods for conveying external time domain information to provide time synchronization. The devices communicate with each other by adjusting their follow-up messages based on the time stamp contained in TSN messages. The system is a transparent clock, and the network clock synchronizes with the GM of the FPGA 5G system.
A translator (UE side) calculates TS_delta and generates a new (g)PTP message. This new PTP message contains the TSN time, correction field values from TSN, and various contributions along the chain. These changes are known as egress from the 5G clock domain. The translator modifies the Ethernet header of the (g)PTP message.
OpenCL can host station functions on FPGA. This technique offsets the CPU core computation by up to 85%. OpenCL can also help host SIMD and HDL-based processing. These techniques improve the performance of vectorized high-end processors. However, achieving these benefits requires a more efficient FPGA platform.
Support for multiple air interfaces
As the physical layer of 5G develops, various candidate technologies are coming up. FPGAs are ideal for evaluating these technologies because they can rapidly implement required algorithms and interfaces while enabling quick design changes. As a result, FPGAs will become a key component of 5G wireless infrastructure prototyping in the next few years. While traditional high-volume ASICs have been helpful for many years, the availability of FPGA technology allows for a new deployment model.
These systems use up to 1024 antennas and enable fine-grain beam-forming and spatial multiplexing. The signal is then focused within each beam, enabling simultaneous transmission over multiple paths. This approach is highly cost-effective and can dramatically reduce the energy needed for FPGA 5G radios. In addition, it will significantly reduce the number of air interfaces and thereby minimize overall system cost.
The FPGA architecture can support multiple waveforms. A new feature called Dynamic Frequency Scaling (DFS) allows for run-time adjustments of processing throughput while minimizing power consumption by up to 88%. In addition, its low reconfiguration latency is only two orders of magnitude below that required for 5G communications. Further, the flexibility of an FPGA design means that we can use it for many applications, including 4G and 5G.
High-performance RF transceiver portfolio
To meet the demands of the FPGA 5G network, RFICs will play an increasingly important role. Besides LTE-Advanced and sub-7GHz band combinations, 5G networks will also require a high-performance mmWave IF transceiver. With a portfolio encompassing a broad range of configurations, RFICs support multiple bandwidths and will be able to meet various spectrum requirements.
The RFFE portfolio includes multiple antenna elements, bands, and carrier aggregation requirements. In addition, ST has designed a complete RF-SOI technology portfolio encompassing the H9SOIFEM node and C65SOIFEM node to meet these demands. These integrated RF solutions are optimized to meet analog RF performance and integration requirements, such as 5G/4G mobile modems and narrowband IoT devices.
Using hardware offloading in FPGAs can reduce the latency of high-speed data communication. These FPGAs can perform various tasks, including compression and decompression, encryption and decryption, data slicing, and deep packet inspection. The Silicom PacketMover FPGA framework simplifies the integration of high-performance networking applications. It is also applicable to monitoring and inline solutions.
During 5G, the spectrum will expand to higher millimeter-wave frequencies, which have never been helpful for cellular communications. This spectrum will require new baseband architectures, beam-forming techniques, and sophisticated RF domain processing. Hardware offloading in FPGAs can help cellular networks address these challenges. However, it will be necessary to develop new processor architectures to handle these frequencies.
With a new approach to virtualization and cloud-native 5G RAN, vendors can optimize the stack for high-speed virtualization. For example, cloud hyperscalers optimized networking, security, and storage virtualization and adopted SmartNICs to offload data-centric workloads to hardware accelerators to accelerate processing. The 5G L1 offload approach uses the same principle. In addition, the Xilinx Accelerated RAN solution leverages Rayming PCB & Assembly technology based on Xilinx FPGAs to achieve the industry-best performance/cost ratio.
Unlike other networking technologies, FPGAs provide complete network hardware disaggregation. Operators can easily select the FPGAs they need for their networks and port IP from one FPGA to another. With this approach, network operators can avoid vendor lock-in and minimize the total cost of ownership. This technology is a valuable component of 5G networks. The advantages of using FPGAs in network edge applications are obvious.
The disaggregation approach to network design and development is an increasingly popular way to meet future needs, especially for the fast-growing 5G industry. This method enables operators to implement open, flexible, and future-proof solutions while maintaining high performance and agility. In addition, disaggregation and FPGAs are key to future-proofing networks. With these advantages, more operators should consider this 5G network design and development approach.
One of the benefits of future-proofing with FPGAs is their ability to run multiple CPUs at once. In addition, these flexible and scalable hardware designs allow for a high number of functions, such as a higher number of cores. Using FPGA technology in network design also allows for creating customized ASICs, ensuring that networks operate smoothly. The UEP-60 is the latest product from Ethernity and is the only NIC of its kind to offer full FPGA-based routing and clock synchronization. Additionally, the ACE-NIC100 is compatible with 5G FEC. Ethernity also partners with customers to customize telecom features on 3rd-party hardware.
The upcoming 5G technology will require increased bandwidth. The current 100/100Mbit/s capability may be sufficient today, but in the future, the available bandwidth could reach up to 10 times the current rate. Further, the 5G deployment process will be staged based on the frequency bands, starting with sub-6GHz frequencies, then moving to contiguous bands using mmWave. The Internet of Things will enable connectivity to many more devices. By 2020, there will be 50 billion cellular-connected devices, which will need higher bandwidth. The existing standards will address this by introducing Massive Machine Type Communications (MMTC).