The MLCC DC bias effect can shrink your 10µF cap to 2µF in circuit. Learn why it happens, which dielectrics suffer most, and how to select and derate correctly.

You pulled up the BOM, confirmed 10µF on the decoupling cap, soldered the board, powered it up — and then spent two days debugging a switching regulator that oscillates at the wrong frequency. The schematic is correct. The layout looks clean. The part number matches. What went wrong?

Almost certainly, it was MLCC DC bias. That 10µF ceramic cap you placed on the 5V rail may be delivering 2–3µF under actual operating conditions. And the datasheet never lied to you — it just measured the capacitance at 0V. You’re running at 5V.

This is one of the most commonly missed phenomena in PCB design, and it bites experienced engineers as often as it catches beginners. This guide explains exactly what MLCC DC bias is, why it happens at the physics level, how badly it affects each dielectric type, and — most importantly — what you can do about it.

What Is MLCC DC Bias and Why Does It Matter?

MLCC DC bias refers to the drop in effective capacitance that occurs when a DC voltage is applied across a Class II multilayer ceramic capacitor. The capacitance value printed on the part — and measured in the datasheet — is tested at essentially zero DC bias, typically using a tiny AC signal of around 0.5–1V RMS at 1 kHz with no DC offset. The moment you put that capacitor into a circuit with a real voltage across it, the actual capacitance begins to fall.

The effect is not subtle. A 4.7µF 25V X5R 0603 MLCC from Murata — the kind of part you’d reasonably use as an output capacitor on a small switching converter — can deliver only about 1.3µF at 10V bias, less than half the rated voltage. At rated voltage, things are worse: a 4.7µF 25V 0805 X5R capacitor operating at its full 25V rating delivers only about 15% of its rated value — around 0.7µF.

For general decoupling on low-voltage rails (3.3V or below), the effect is manageable but still real. For output filters on buck converters, charge pump circuits, RC timing networks, and precision analog applications, ignoring MLCC DC bias is a design error that will cost you at board bring-up or, worse, in the field.

The Physics Behind MLCC DC Bias: Ferroelectric Dipoles

To understand why this happens, you need to look at what’s inside a Class II MLCC.

Class I vs Class II Dielectrics

Class I MLCCs use titanium dioxide (TiO₂) as the dielectric material. Class II MLCCs use barium titanate (BaTiO₃) along with additives. Class I types are more stable but are limited to lower capacitance values. Class II capacitors have higher volumetric efficiency — and that’s where the DC bias problem lives.

The EIA coding tells you which class you’re dealing with. If the temperature characteristic code starts with C, H, or P (like C0G or NP0), it’s Class I and has no meaningful DC bias effect. If it starts with X, Y, or Z (X5R, X7R, Y5V, Z5U), it’s Class II and DC bias is a real concern.

Why Ferroelectric Materials Lose Capacitance Under Voltage

Barium titanate has a tetragonal crystal structure below its Curie temperature of approximately 125°C. This structure generates electrical dipoles — one side of each crystal axis is more positive and the other more negative. Without any applied DC voltage, these dipoles arrange themselves randomly throughout the crystal structure, resulting in high dielectric constant and high capacitance.

When a DC voltage is applied, the resulting electric field begins to align the dipoles parallel to the field. Some dipoles align at low voltages; more align as voltage increases. The progressive alignment of dipoles reduces the dielectric constant, and capacitance falls continuously as voltage rises. At the full rated voltage, capacitance can drop by 50% or more from the zero-bias nominal value.

The problem has gotten significantly worse in modern high-density MLCCs. To achieve higher capacitance in a given package size, manufacturers either increase the dielectric constant of the ceramic material or increase the number of dielectric layers by making each layer thinner. Both approaches amplify the DC bias effect. Thinner dielectric layers mean a given terminal voltage creates a stronger electric field per unit thickness across the dielectric, increasing the bias-induced dipole alignment.

The Hysteresis Problem

There is an additional subtlety that complicates the picture: the DC bias effect can exhibit hysteresis, because the ferroelectric material has a hysteretic polarization-electric field curve. In practical terms, this means the effective capacitance at a given voltage can differ depending on whether you’re sweeping voltage up or down, and it can also vary with the history of voltage stress applied to the part. Lab measurements and manufacturer simulation tools show this behavior, and it means the real capacitance in a circuit with dynamic voltage swings is even harder to predict than a static DC bias curve suggests.

How Bad Is It? Real-World Capacitance Loss Data

The numbers, once you look at them carefully, are genuinely alarming for anyone who has been selecting ceramic capacitors purely by the nominal value.

Worked Example: The 10µF That Became 2µF

Consider an X5R 0805 10µF 6.3V capacitor used as a 5V coupling capacitor in an operational amplifier application. The combined capacitance loss factors include: approximately 60% loss of capacitance from the 5V DC bias (close to the 6.3V rated voltage), about 15% additional loss from the AC voltage component, 10% loss due to operating temperature, and 5% per decade of time from aging. The total actual capacitance is the product of all these individual loss factors — not their sum. The expected actual capacitance in this operating condition is approximately 2.9µF, and in worst-case scenarios for different part numbers and manufacturers, the real capacitance can be as low as 10% of the rated value.

That’s the headline: a labeled 10µF capacitor providing somewhere between 1µF and 3µF in a real circuit. Every factor multiplies against the others.

Capacitance Loss by Dielectric Type: A Comparison

The severity of MLCC DC bias varies significantly by dielectric class. This table summarizes typical worst-case capacitance retention at various percentages of rated voltage:

Dielectric	At 25% Rated Voltage	At 50% Rated Voltage	At 80% Rated Voltage	At 100% Rated Voltage
C0G (NP0) – Class I	~100%	~100%	~100%	~100%
X7R – Class II	~85–90%	~60–75%	~40–55%	~30–50%
X5R – Class II	~80–85%	~50–70%	~30–40%	~15–30%
Y5V – Class II	~70%	~30–50%	~10–20%	<10%

Note: Values are representative ranges based on published manufacturer data. Actual loss is part-number specific — always check the DC bias curve for your specific component.

The DC bias effect can shrink capacitance anywhere from 10% to 90% at rated voltage for ferroelectric MLCCs. Y5V dielectrics are effectively unsuitable for any application where stable capacitance matters.

How Package Size Affects DC Bias

Capacitance loss due to DC bias can be reduced by using a physically larger case size, because a larger case reduces the electric field strength (V/mm) across the dielectric material. A 10µF 6.3V X5R capacitor in an 0805 package shows significantly less capacitance loss at a given voltage than the same nominal value in an 0603 package.

Since the DC bias effect is directly related to the size of the dielectric, the smaller the capacitor footprint, the worse it performs. This has a counterintuitive implication: the trend toward smaller passive components directly worsens DC bias-induced capacitance loss for any given nominal capacitance value.

For a 1µF capacitor featuring a nominal voltage of 25V, the capacitance at 10V only decreases by about 2%, because the dielectric layers are thicker at higher nominal voltages. Thicker dielectric means a weaker electric field per layer, affecting fewer dipoles.

DC Bias Plus Aging: The Compounding Effect

MLCC DC bias does not operate in isolation. It compounds with two other degradation mechanisms that every PCB engineer should understand: thermal capacitance change and dielectric aging.

MLCC Aging (Time-Related Capacitance Drift)

All Class II ceramic capacitors lose capacitance over time even at room temperature, even at zero voltage, because the ferroelectric grains slowly transition to more energetically stable crystal domain configurations. This process is called aging. The standard model for aging is roughly 5% capacitance loss per decade of time (per decade of hours: after 10 hours, after 100 hours, after 1000 hours, etc.).

Recent research has found that prolonged exposure of X7R capacitors to a DC bias voltage leads to capacitance decrease much stronger than the natural aging drift alone. In competitive testing of multiple vendor X7R parts, all competing capacitors showed greater-than-specified rates of capacitance loss over time under bias conditions. After 1000 hours of bias exposure, all competing MLCCs tested lost more than 20% of their capacitance beyond the initial DC bias effect.

This DC bias aging effect was not widely recognized until automotive manufacturers began reporting failures in critical systems. The capacitance loss from DC bias aging is not simply additive with the instantaneous DC bias effect — the two compound multiplicatively.

Temperature and DC Bias Together

The temperature coefficient of capacitance for X7R is specified as ±15% over the rated temperature range, and X5R is similar within its narrower range. When thermal reduction and DC bias reduction occur simultaneously, the combined loss is again multiplicative, not additive.

For X5R operating at 50% of rated voltage and 85°C, assume only 40–50% of rated capacitance will actually be available. Combined with aging and DC bias, an X5R “10µF” capacitor might deliver only 3µF under worst-case conditions.

Which Circuits Are Most Affected by MLCC DC Bias?

Switching Regulator Output Filters

The entire control loop for a buck or boost converter depends on a certain amount of capacitance. If the design is based on nominal capacitance values, DC bias can cause stability problems or EMC issues. This is especially pronounced on the input of a buck converter and the output of a boost converter, where voltages are highest. Many IC datasheets for switching regulators do not explicitly state whether the required capacitance is nominal or effective, leaving the designer to discover the discrepancy through board-level testing.

Charge Pump Circuits

Charge pumps place DC voltages across their capacitors — including the flying capacitor used to transfer charge and the input and output capacitors. All of these are directly affected by DC bias. The real capacitance directly impacts charge pump performance, and a significant reduction in effective capacitance translates directly to reduced output current capability.

RC Timing Circuits

An engineer designing an RC time delay circuit using a large ceramic capacitor in series with a large resistor will find that the actual time constant is not simply R × C_nominal. Because capacitance decreases with bias voltage during the charging cycle, the RC time constant is effectively some smaller and voltage-dependent value. The actual time delay requires integrating the DC bias-capacitance curve, not simply multiplying the nominal values.

Precision Analog and Audio Circuits

For analog signal paths using large ceramic capacitors as DC blocking or coupling capacitors, MLCC DC bias creates a voltage-dependent capacitance that can introduce nonlinearity and distortion. In audio circuits, this nonlinearity is audible. Additionally, Class II ceramics exhibit piezoelectric behavior — physical vibration induces voltage and vice versa — causing acoustic noise in power circuits and susceptibility to microphonics in sensitive analog paths.

How to Fix MLCC DC Bias: Practical Solutions for PCB Engineers

Solution 1: Use the Manufacturer’s DC Bias Simulation Tools

Before you finalize any MLCC selection where DC bias matters, check the actual effective capacitance at your operating voltage using manufacturer tools. This is not optional for switching converter filters, charge pumps, or RC timing applications.

The key tools are listed in the resources section below. Murata SimSurfing is the most widely recommended — it lets you enter operating voltage, temperature, and frequency to get the actual effective capacitance curve, not just the nominal value.

Solution 2: Select a Higher Voltage Rating

Using capacitors with a higher voltage rating than strictly required can offset the DC bias capacitance reduction. A capacitor operating at a lower percentage of its rated voltage retains more of its nominal capacitance. For a 1µF capacitor rated at 25V, the capacitance at 10V only decreases by about 2% — because higher voltage ratings use thicker dielectric layers, which produce a weaker electric field per layer at the same terminal voltage.

As a practical rule, select an MLCC with a voltage rating at least 2× your operating voltage for X7R parts and 3× for X5R parts if you need reasonably stable effective capacitance.

Solution 3: Use a Larger Physical Package

A physically larger case size design reduces the V/mm electrical field exposed to the dielectric. A 10µF X5R in an 0805 package shows significantly better DC bias behavior than the same value in a 0603 package. If board space allows, stepping up a package size is often the lowest-cost fix.

Solution 4: Upgrade the Dielectric Grade

Moving from X5R to X7R, from X7R to X8R, or to tighter tolerance grades such as X7P reduces DC bias sensitivity. The higher-grade dielectrics use ceramic formulations with less ferroelectric character, trading some volumetric efficiency for better stability.

Solution 5: Parallel Multiple Smaller Capacitors

Two capacitors connected in parallel with lower individual capacitance values — each with thicker dielectric layers — can achieve the same total nominal capacitance with better DC bias behavior than a single higher-value part in the same package. For example, two 4.7µF parts may outperform a single 10µF part in effective capacitance under bias, because the lower capacitance value requires thicker dielectric layers.

Solution 6: Switch Capacitor Technology

For applications where MLCC DC bias is genuinely unacceptable — precision timing, stable analog filtering, high-reliability industrial or automotive designs — consider switching away from Class II ceramics entirely for those specific positions.

Capacitor Type	DC Bias Effect	Best Use Case
C0G / NP0 MLCC	None	Tuned circuits, RF, precision timing, oscillators
X7R MLCC	Moderate (better than X5R)	General decoupling, low-to-mid voltage rails
X5R MLCC	Significant	High-capacitance density, low-voltage rails only
Polymer Tantalum	Negligible	Stable bulk capacitance, medium voltage
Aluminum Electrolytic	Negligible (but polarized)	Bulk filtering, high capacitance values
Film (Polypropylene)	None	AC filtering, precision analog, high voltage

Polymer tantalum and aluminum hybrid capacitors can be good alternatives when DC bias stability is required but board space does not allow larger MLCC packages.

Comparing Dielectrics: DC Bias Performance at a Glance

This table summarizes the key trade-offs between the most common MLCC dielectric types relevant to the DC bias decision:

Parameter	C0G (NP0)	X7R	X5R	Y5V
EIA Class	I	II	II	II
Dielectric material	TiO₂	BaTiO₃ + additives	BaTiO₃ + additives	BaTiO₃ (high-K)
DC bias effect	Essentially none	Moderate	Significant	Severe
Temp coefficient	±30 ppm/°C	±15% (−55 to +125°C)	±15% (−55 to +85°C)	+22%/−82%
Max capacitance per package	Low	Medium	High	Very high
Aging	Negligible	~1–5%/decade	~1–5%/decade	>5%/decade
Recommended for DC voltage circuits	Yes	Yes (check DC bias curves)	With caution	Avoid

Vendor Differences: Not All X7R Parts Are Equal

One aspect of MLCC DC bias that catches engineers off guard when qualifying alternative sources: the same part number from a different manufacturer can have meaningfully different DC bias behavior. Qualifying a new vendor using a part at different application conditions without background knowledge of the DC bias data can lead to catastrophic system failures. In one documented case, three different manufacturers’ versions of the same 10µF 6.3V X5R MLCC showed very different capacitance drop curves over time under bias, with a substitute vendor added during a shortage situation resulting in field failures.

Measured vendor data and simulated vendor data can differ significantly. In comparative testing across multiple vendors, some manufacturers’ simulation tools underestimated the actual capacitance loss, meaning real-world performance was worse than the tool predicted.

The practical implication: whenever you qualify a new MLCC source, re-verify the DC bias performance against your actual operating conditions, not just the nominal capacitance specification.

Step-by-Step: How to Select an MLCC Accounting for DC Bias

Here is a practical workflow for any application where DC bias could matter:

Step	Action	Tool/Reference
1	Identify the DC operating voltage across the capacitor	Circuit schematic, simulation
2	Identify operating temperature range	System thermal analysis
3	Look up the DC bias derating curve for the candidate part	Manufacturer simulation tool (SimSurfing, K-SIM, etc.)
4	Determine effective capacitance at operating V and T	Read from the curve at your operating point
5	Check if effective capacitance meets circuit requirements	Compare to required value
6	If not, select higher voltage rating, larger package, or better dielectric	Iterate
7	Re-verify effective capacitance for the new candidate part	Repeat step 3–4
8	Include aging margin (5–10% additional derating) for long-life designs	Apply to final selection

For capacitors used in switching regulator output filters, confirm with the IC manufacturer whether the required capacitance in the datasheet refers to nominal or effective capacitance. Many power management IC datasheets specify effective capacitance — if the MLCC selection is based on nominal value alone, the actual loop bandwidth and stability margin will be different from what was designed.

Useful Resources for MLCC DC Bias Research

These tools and documents are directly applicable to real design decisions:

Resource	Type	Why It’s Useful
Murata SimSurfing	Online simulation tool	The industry standard — enter voltage, temperature, frequency to get effective capacitance curve for any Murata MLCC
TDK Product Advisor	Component database	DC bias curves and temperature characteristics for TDK MLCCs
Kemet K-SIM	SPICE simulation	Full MLCC SPICE models including DC bias behavior
Samsung Electro-Mechanics SPEC	Component database	DC bias and aging data for SEMCO MLCCs including X7S parts
EPCI Article: High CV MLCC DC Bias and Ageing Explained	Technical article	Comprehensive treatment of DC bias + aging interaction with real data
Vishay DC Bias Aging Study (PDF)	Technical paper	Comparative data on X7R DC bias aging across multiple vendors
OS Engineering DC Bias Measurement Study (PDF)	Technical paper	Independent measured DC bias data including hysteresis effects
KYOCERA AVX DC Bias App Note (PDF)	Application note	Physics explanation and selection guidance from an MLCC manufacturer
Manufacturer datasheets	Primary source	Always check the voltage vs. capacitance curve for your specific part number

FAQs: MLCC DC Bias

Q1: Does the ±10% or ±20% tolerance marking on an MLCC capacitor include the DC bias effect?

No, and this is one of the most common misconceptions. The temperature rating code (like X7R with ±15% tolerance) covers variation due to temperature change only. It tells us absolutely nothing about the DC bias effects. The tolerance marking reflects capacitance variation from the nominal measured at zero bias and rated temperature. The DC bias-induced capacitance loss is entirely separate and is not captured in the standard tolerance specification.

Q2: Does MLCC DC bias affect C0G (NP0) capacitors?

No. C0G is a Class I dielectric using titanium dioxide, which is not ferroelectric. It does not exhibit voltage-dependent polarization and has essentially zero DC bias effect. The trade-off is that C0G ceramics have much lower dielectric constants, which limits the available capacitance per package size. C0G parts are typically available up to a few µF in larger packages, making them suitable for precision applications but impractical for bulk decoupling requiring tens of µF.

Q3: If I use a 10V MLCC on a 3.3V rail, is the DC bias effect negligible?

Better than using a 6.3V part, but not negligible — especially for X5R. At 33% of rated voltage (3.3V on a 10V part), an X5R capacitor might still lose 20–30% of its nominal capacitance. An X7R at the same operating point would lose perhaps 10–20%. For general decoupling this is often acceptable. For precision applications, RC timing, or converter output filters, always verify using the manufacturer’s simulation tool. Using a 16V or 25V rated part on a 3.3V rail gives significantly better effective capacitance retention.

Q4: My switching regulator is unstable — could MLCC DC bias be the cause?

Yes, and it’s more common than most engineers expect. The DC bias issue with buck and boost regulators is particularly serious because many IC datasheets for these devices do not clearly state whether the required output capacitance is nominal or effective. The distinction can lead to an 80% difference in actual capacitance, which directly affects control loop crossover frequency and phase margin. If your regulator oscillates or has poor transient response, verify the effective capacitance of your output filter MLCCs at the output voltage using SimSurfing or K-SIM, and compare it to what the IC datasheet actually requires.

Q5: I need to replace an MLCC with an alternative source — do I need to re-test DC bias performance?

Yes, always. The DC bias effect is dependent on various parameters that are internal to the specific part number and manufacturer design — it is not guaranteed to be identical across different manufacturers even for nominally equivalent parts. MLCC DC bias behavior is not covered by standard part-equivalency assumptions. When qualifying an alternative source for any position where effective capacitance under bias is critical — switching converter filters, timing circuits, charge pumps — re-verify the DC bias curve against your operating conditions before approving the substitution.

Summary: What Every PCB Engineer Should Remember About MLCC DC Bias

MLCC DC bias is not an obscure corner case — it’s a fundamental characteristic of every Class II ceramic capacitor, and it affects every circuit where those capacitors see a significant DC voltage. The nominal capacitance is measured at zero voltage and is essentially a marketing number for real power circuits.

The practical rules to take away from this: always pull the DC bias derating curve from the manufacturer’s simulation tool before finalizing an MLCC selection for any voltage-sensitive application; select voltage ratings at least 2× the operating voltage to retain meaningful capacitance; prefer X7R over X5R where board space allows a higher-voltage or larger-package part; use C0G for anything where stable capacitance is genuinely critical; and treat aging plus DC bias as compounding, multiplicative effects — not additive ones.

Every one of these decisions costs pennies at the component level. Ignoring them can cost days of debug time, board respins, or field failures that trace back to a labeled 10µF capacitor that was actually running at 2µF.