Learn how to design a capacitor bank correctly — covering parallel and series configurations, DC link sizing, PFC resonance risks, current sharing, anti-resonance, inrush protection, and PCB layout rules. With formulas, tables, and a full FAQ.

Every experienced PCB engineer has made this mistake at least once: you need more bulk capacitance on a DC rail, you grab three identical electrolytics, solder them in parallel, and call it done. The schematic is clean. The math looks right. Then the board comes back from test with a 200 mV ripple spike you cannot explain — or worse, two of the three capacitors are running noticeably hotter than the third.

Paralleling capacitors is not as simple as adding microfarads together on paper. A capacitor bank introduces current sharing problems, parasitic resonances, inrush events, and layout-driven impedance imbalances that a single capacitor never has to deal with. This guide covers everything from the fundamental math to the practical PCB layout decisions and protection requirements that separate a reliable capacitor bank design from one that causes intermittent field failures.

What Is a Capacitor Bank and When Do You Need One?

A capacitor bank is a group of capacitors connected in parallel, series, or a series-parallel combination to achieve a voltage rating, capacitance value, or current-handling capability that a single capacitor cannot deliver on its own.

In practical terms, you build a capacitor bank when:

• No single capacitor in the right package provides the total capacitance you need
• The ripple current requirement exceeds what one capacitor can handle thermally
• You need lower effective ESL than any single large capacitor can achieve
• The bus voltage exceeds the rating of available single-unit capacitors (requiring series banks)
• You need redundancy — continued operation if one unit fails

Capacitor banks appear across an enormous range of power levels: from a cluster of MLCCs on a microcontroller’s VCC pin all the way up to multi-megavar PFC installations correcting power factor for an entire manufacturing plant. The physics are the same. The design discipline scales.

Capacitor Bank Fundamentals: Series vs. Parallel Configurations

Before getting into layout and protection, it helps to have the formulas and trade-offs clearly in one place.

Parallel Capacitor Bank

When capacitors are connected in parallel, all positive terminals share one node and all negative (or return) terminals share the other. Every capacitor sees the same voltage.

Total capacitance:

C_total = C₁ + C₂ + C₃ + … + Cₙ

Total ESR: (parallel combination, like resistors in parallel)

ESR_total = 1 / (1/ESR₁ + 1/ESR₂ + … + 1/ESRₙ)

Total ESL: (parallel combination)

ESL_total = 1 / (1/ESL₁ + 1/ESL₂ + … + 1/ESLₙ)

Paralleling capacitors adds capacitance, reduces ESR, and reduces ESL. For most power electronics applications, this is the desired outcome.

Series Capacitor Bank

Capacitors in series share the same charge but divide the voltage. Capacitance decreases while voltage rating increases.

Total capacitance:

1/C_total = 1/C₁ + 1/C₂ + … + 1/Cₙ

For identical capacitors in series: C_total = C_unit / n

Total voltage rating: approximately V_total = V_unit × n (with balancing)

Series banks are used when bus voltage exceeds what individual capacitors can withstand — common in high-voltage DC links, traction inverters, and utility-scale PFC systems. Voltage sharing between series capacitors is never perfectly equal in practice, which introduces a balancing resistor requirement covered later in this guide.

Series-Parallel Combined Bank

The full series-parallel configuration provides the most flexibility. For a bank of m rows of n capacitors in series, each capacitor rated at C_unit and V_unit:

C_total = (m × C_unit) / n V_total ≈ n × V_unit

This approach allows the designer to independently target total capacitance, total voltage rating, and current handling capability by adjusting the row and column count.

Configuration Summary Table

Configuration	Capacitance	Voltage Rating	ESR	ESL	Primary Use
Parallel only	Increases (sum)	Same as one unit	Decreases	Decreases	DC link, decoupling, bulk rail
Series only	Decreases (1/n)	Multiplied by n	Increases	Increases	High-voltage DC links
Series-parallel	Tunable	Tunable	Tunable	Tunable	Industrial PFC, inverter DC bus

Capacitor Bank Applications: Matching Design to Use Case

DC Link Capacitor Bank (Inverter and Motor Drive)

The DC link capacitor bank is one of the most common and demanding applications in power electronics. In a PWM inverter — whether driving a motor, a UPS output stage, or a grid-tie converter — the DC link capacitor bank performs two simultaneous jobs:

1. Voltage stiffening: The bank decouples the effects of stray inductance in the DC cable or bus bar. Any inductance between the DC source and the inverter bridge will cause voltage spikes during switching transitions. The capacitor bank sits directly across the inverter input and provides the instantaneous current the switches demand, preventing the DC bus from collapsing under each switching event.

2. Ripple current absorption: PWM switching generates AC ripple current components at multiples of the switching frequency. The capacitor bank absorbs these ripple currents through its internal ESR, which is why ripple current rating — not capacitance alone — is often the dimensioning constraint for DC link banks.

For DC link design, the minimum capacitance is estimated from the allowable DC bus ripple voltage:

C_min = I_load / (f_sw × ΔV_bus)

Where f_sw is switching frequency and ΔV_bus is the maximum allowable peak-to-peak bus ripple (commonly specified as 1–5% of bus voltage). Ripple current through the bank at peak load must then be checked against the combined ripple current rating of the paralleled capacitors, since ripple current thermal stress — not capacitance value — typically drives component selection and quantity.

Power Factor Correction (PFC) Capacitor Bank

In AC systems, capacitor banks supply reactive power to counteract inductive loads. Inductive loads (motors, transformers) draw reactive current that circulates in the wiring and transformer without doing useful work, lowering the power factor and forcing the utility to oversize distribution equipment.

The reactive power a capacitor bank must provide is calculated from:

Q_C (kVAR) = P × (tan φ₁ − tan φ₂)

Where P is active load power in kW, φ₁ is the existing power factor angle, and φ₂ is the target power factor angle. Most utility tariffs impose penalties below power factor 0.9, making PFC economically mandatory in most industrial facilities.

Harmonic resonance is the dominant failure risk in PFC banks. Modern facilities with variable frequency drives, switching power supplies, and rectifiers generate harmonic currents — particularly the 5th (250/300 Hz), 7th (350/420 Hz), and 11th harmonics. If the PFC bank’s natural resonant frequency coincides with a dominant harmonic, current amplification can destroy the capacitor bank within hours. The resonant frequency is:

f_res = f_fundamental × √(kVA_sc / kVAR_bank)

Any facility where non-linear loads represent more than 20% of total load should use detuned reactors (series inductors) to shift the resonant frequency below the lowest significant harmonic — typically tuned to 189 Hz (4.7th harmonic) for 60 Hz systems.

PCB-Level Decoupling Capacitor Bank

At the circuit board level, a capacitor bank is the standard architecture for power delivery network (PDN) decoupling. The strategy is to cover a broad frequency range with capacitors of different values and types placed at different distances from the load:

Stage	Capacitor Type	Value Range	Location	Purpose
Bulk	Electrolytic or tantalum	47–470 µF	Near power entry point	Low-frequency ripple, bulk charge reservoir
Intermediate	MLCC (X5R/X7R)	1–22 µF	Near device clusters	Mid-frequency transient response
High-frequency	MLCC (X7R/C0G)	10–100 nF	At IC power pins	High-frequency switching noise
Ultra-HF	MLCC (C0G)	100 pF – 1 nF	Directly at IC pins	Multi-hundred MHz decoupling

For a thorough discussion of how capacitor dielectric type, package geometry, and mounting affect performance in PCB-level bank designs, the detailed reference on PCB capacitors covers the key characteristics that scale from discrete circuit-board applications all the way up to power converter design.

The Critical Problems with Paralleling Capacitors

This is where most designs run into trouble. The equations say capacitance adds up and ESR and ESL divide — but only if current shares equally between all paralleled units. In practice, current sharing is almost never equal unless the layout enforces it.

Unequal Current Sharing Due to Layout Asymmetry

Current follows the path of lowest impedance. In a parallel capacitor bank, the capacitor physically closest to the switching node will have a shorter current path and lower parasitic inductance in its loop. That unit sees higher peak currents, higher ripple current, and higher thermal stress than the units further from the source.

Bus bars or PCB traces connecting parallel capacitors must have equal impedance to each unit. Unequal trace lengths cause unequal current sharing, concentrating stress on the closest capacitors. Symmetrical star or balanced bus bar layouts are essential.

This is not theoretical. In high-ripple-current applications (DC link banks, gate drive bypass banks), a layout-asymmetric bank can fail one capacitor every few months while the others appear fine. The root cause is always the same: unequal loop inductance in the parallel paths.

ESR Mismatch Between Parallel Units

The ripple current divides inversely proportional to ESR — a unit with lower ESR carries more current and runs hotter. In practice, use the same manufacturer, part number, and production lot for all paralleled capacitors.

Even capacitors from the same production run have ESR variation within the manufacturer’s tolerance. A capacitor whose ESR is 20% below its nominal value will carry 20% more ripple current than its neighbors. Over thousands of hours at elevated temperature, this becomes a life-limiting factor.

Anti-Resonance Between Parallel Capacitors of Different Values

When capacitors of different values are placed in parallel — as in a multi-stage PDN decoupling bank — their different self-resonant frequencies interact and can produce an anti-resonance peak: a frequency at which the combined impedance is actually higher than either capacitor alone. This happens when one capacitor’s inductive region overlaps with the other’s capacitive region at the same frequency.

Anti-resonance is the reason you cannot simply stack up a large electrolytic and several small ceramics and call it a broadband solution. The interaction between them at the transition frequency creates a local impedance peak that can amplify noise rather than suppress it. The solution is to:

• Simulate the combined impedance across frequency before finalizing values (SPICE or dedicated PDN simulators)
• Use capacitors whose self-resonant frequencies are well separated so the resonance interaction falls outside the critical frequency range
• Add a small resistor (0.1–1 Ω) in series with the larger capacitors to damp the resonance without significantly affecting its capacitive performance

Inrush Current on Power-Up

When a capacitor bank powers up into a discharged state, it looks momentarily like a short circuit. The inrush current is limited only by the source impedance and the ESR plus loop inductance of the bank:

I_peak ≈ V_bus / (ESR_bank + R_source)

For a large DC link bank at 400–800 V bus with very low ESR film capacitors, this peak inrush can reach tens of kiloamperes — enough to weld relay contacts, blow fuses, and destroy bridge rectifier diodes. Pre-charge circuits are mandatory for any capacitor bank above a few hundred microfarads at voltages above 48 V.

The standard pre-charge approach places a resistor in series with the rectifier input. The resistor limits inrush current during initial charge-up; a bypass contactor then shorts around it once the bus voltage reaches approximately 80% of nominal. Sizing the pre-charge resistor:

R_precharge = V_bus / I_max_inrush P_R ≥ (½ × C_bank × V²_bus) / t_precharge

Where t_precharge is the time allowed for the bus to charge.

Voltage Balancing in Series Capacitor Banks

Connecting capacitors in series for high-voltage applications introduces a voltage sharing problem that can kill capacitors even when the total bank voltage is well within spec.

In theory, identical series capacitors share voltage equally. In practice, manufacturing tolerances in capacitance value, leakage current, and dielectric absorption all cause unequal voltage distribution. The capacitor with the lowest leakage current will charge to the highest voltage. If that overvoltage exceeds the unit’s rating, it fails — and its failure immediately stresses the remaining capacitors.

The fix is balancing resistors — one resistor in parallel with each series capacitor — sized to dominate the voltage distribution by providing a consistent parallel leakage path:

R_balance = V_working / (10 × I_leakage_max)

A typical balancing resistor value for a series bank of electrolytics is 10–100 kΩ depending on working voltage. A bleeder effect — the bank discharges through the balancing resistors when power is removed — is a side benefit, though for safety-critical applications an explicit discharge circuit is still required.

PCB Layout Rules for Capacitor Bank Design

The layout is where the design either works or fails. Every calculation above assumes an idealized circuit — the layout determines how close you get to that ideal.

Symmetrical Layout: The Single Most Important Rule

Every parallel capacitor in a bank should have the same electrical path length from the source to its positive terminal and from its negative terminal back to the return. Star topology — where each capacitor connects back to a central bus point via equal-length traces — is the textbook approach.

Minimize Loop Area in Each Capacitor’s Current Path

Loop area drives parasitic inductance. Keep the positive and negative traces of each capacitor’s current loop as close together as possible (ideally on adjacent PCB layers with overlapping copper planes) to cancel mutual inductance through proximity.

Via Placement for Capacitor Banks

Each capacitor in a bank should have its own dedicated vias to the power and ground planes. Sharing vias with adjacent capacitors introduces common-impedance coupling — a current event in one capacitor’s loop appears in its neighbor’s loop through the shared via inductance. As a rule, never share a via between two capacitors in the same bank.

Capacitor Placement Relative to Load

For PCB-level decoupling banks, placement priority is clear: smallest-value, highest-frequency capacitors go closest to the IC power pins. Larger-value bulk capacitors go further away. This ensures the fastest-responding capacitors have the shortest loop inductance to the point of current demand.

Layout Best Practices Summary

Layout Decision	Correct Practice	Why It Matters
Trace length to parallel caps	Equal length to all units	Forces equal current sharing
Trace width	Maximize for current-carrying traces	Reduces trace resistance and inductance
Via placement	Dedicated vias per capacitor	Avoids shared-impedance coupling
Layer stackup	Power and ground planes adjacent	Minimizes loop inductance via flux cancellation
Capacitor orientation	Align pads along current flow direction	Reduces package ESL contribution
Distance from switch node	Minimize for high-frequency caps	Shorter path = lower impedance at frequency

Capacitor Type Selection for Bank Applications

Not every capacitor type is suited to bank duty. The correct choice depends on the application’s frequency range, voltage, temperature, and expected service life.

Capacitor Type	Best Bank Application	Key Strength	Key Limitation
Aluminum electrolytic	Bulk DC link, low-frequency rail	High capacitance/volume, low cost	Limited ripple current, temperature-sensitive life
Polypropylene film	High-power DC link, PFC, snubber	Low ESR/ESL, self-healing, long life	Larger volume per µF than electrolytic
MLCC (X7R)	PCB decoupling, high-frequency bank	Tiny size, very low ESL	Capacitance drops with DC bias voltage
MLCC (C0G/NP0)	Ultra-high-frequency precision bank	Stable capacitance, very low loss	Lower maximum capacitance per package
Supercapacitor (EDLC)	Energy storage banks, holdup	Extremely high capacitance	Low voltage rating; ESR not suitable for fast switching

Protection and Safety Requirements for Capacitor Banks

Discharge Resistors

A charged capacitor bank is an electrocution hazard and a source of destructive fault energy. Every capacitor bank above a few joules of stored energy — calculated as E = ½ × C × V² — should include bleed-down resistors sized to discharge the bank to safe voltage within a defined time after power removal. A typical target is to reach below 50 V within 5 seconds for operator safety.

Overcurrent Protection

Individual fuses or overcurrent relays protect against cascade failure. If one capacitor in a parallel bank fails short, it can absorb enough energy from the remaining capacitors to explode. IEC 60831-1 requires PFC capacitor bank protection to trip if current exceeds 1.3× rated current. For DC link banks, individual fusing of each capacitor branch in high-power designs allows a single failed unit to be isolated without taking down the entire bank.

Thermal Monitoring

Temperature is the dominant life-determining factor for both electrolytic and film capacitors. A 10°C rise above rated temperature roughly halves electrolytic capacitor life. For high-power banks in thermally challenging environments, thermocouple or IR thermography checks during commissioning are strongly recommended. Banks installed adjacent to heat sinks or in poorly ventilated enclosures will fail years ahead of their design life.

Useful Resources for Capacitor Bank Design

Resource	Type	Link
Specap — Capacitor Bank Design & Sizing Guide	Comprehensive Design Guide	specap.com
Cornell Dubilier — Selecting and Applying DC Link Bus Capacitors	Technical Paper	cde.com PDF
Eaton — Capacitor Bank Protection Design White Paper	White Paper	eaton.com PDF
Eaton — Inrush Currents in Single and Multi-Step Capacitor Banks	Technical Document	eaton.com PDF
Electronics Tutorials — Capacitors in Parallel	Tutorial Reference	electronics-tutorials.ws
Specter Engineering — Inverter DC Link Capacitor Selection	Practical Design Guide	specterengineering.com
EEP — Capacitor Bank PFC Calculation and Schematics	Electrical Engineering Guide	electrical-engineering-portal.com
Wevolver — Capacitors in Parallel: Theory, Design, Implementation	Deep-Dive Article	wevolver.com

Frequently Asked Questions About Capacitor Bank Design

Q1: How many capacitors should I put in parallel for a DC link bank?

Start with the ripple current requirement, not the capacitance requirement — ripple current is almost always the binding constraint. Divide the total required ripple current rating by the per-unit ripple current rating at your switching frequency and operating temperature. That gives you the minimum parallel count. Then verify the total capacitance meets your bus ripple voltage specification. Add one extra unit if the ripple current is within 10% of the limit, since any production variation in ESR will cause current concentration in the lower-ESR unit.

Q2: Can I mix different capacitor brands or production lots in the same parallel bank?

Technically yes for capacitance; practically problematic for ripple current sharing. ESR variation between different manufacturers or production dates can exceed 30%. Since ripple current divides inversely with ESR, a low-ESR unit in a mixed bank will carry disproportionately higher current and run hotter. For anything other than a low-stress bulk bypass application, use the same manufacturer, part number, and ideally the same production lot for all paralleled units in a power bank.

Q3: Why does my capacitor bank ring after each switching event despite correct component values?

Ringing after switching is almost always caused by the capacitor bank’s combined ESL forming an LC tank with the switch node’s stray inductance. If the ringing frequency is above a few MHz, the loop inductance in your capacitor bank layout is the primary culprit — not the components themselves. Check whether your capacitor placement is truly symmetric, whether you have dedicated vias, and whether any long narrow traces exist between the capacitor bank and the switch terminals. Adding a small RC snubber (typically 1–10 Ω in series with 10–100 nF) directly across the switch node will damp the ringing while you optimize the layout.

Q4: Do I need balancing resistors when paralleling capacitors?

No — balancing resistors are only required for series-connected capacitor banks. In a parallel bank, all capacitors share the same terminal voltage automatically. Balancing resistors in a parallel bank serve only as bleeder resistors (discharge paths), not for voltage equalization. However, if your parallel bank also contains units wired in series for higher voltage rating (a series-parallel bank), then the series strings within the bank do require balancing resistors.

Q5: At what energy level does a capacitor bank require a pre-charge circuit?

There is no universally mandated threshold, but practical experience sets the bar at approximately 1 joule stored energy at voltages above 48 V as the point where uncontrolled inrush starts risking component damage. For automotive and industrial inverter applications, pre-charge is essentially universal for any bank above 100 µF at bus voltages above 100 V. The calculation is straightforward: E = ½ × C × V². A 2,000 µF bank at 400 V stores 160 joules — enough to cause severe arc flash on any connector or relay contact that closes into it without pre-charge current limiting.

Putting It All Together

A well-designed capacitor bank is not a shortcut to more capacitance — it’s a system design challenge that touches layout symmetry, ESR matching, resonance management, inrush protection, and thermal planning simultaneously. The parallel combination formulas are the easy part. The hard part is ensuring that what you draw on the schematic is what the physics actually sees on the board or in the power cabinet.

Use identical components from the same lot. Make your layout symmetric. Keep loop areas small and via counts equal between parallel paths. Pre-charge high-voltage banks. Plan for thermal stress, not just rated temperature. And when you’re not certain whether your PDN impedance is flat enough across frequency, run the simulation — it is always cheaper to fix in software than in hardware.