As the 5G millimeter wave is expected to enter commercial use,In the industry the research and development of key companies is progressing well, and the specification, design and verification of customized component indicators have been completed. The basic component required to implement future millimeter-wave 5G systems is the RF Front End Module (FEM). The module includes the final amplification stage of the transmitter and the front-end amplification stage and the transmit/receive switch (Tx/Rx) in the receiver to support Time Division Duplex (TDD). The FEM must have high linearity in transmit mode and a low noise figure in receive mode. Since the millimeter wave 5G system may require the user terminal to use multiple FEMs to form a phased array architecture or a switched antenna beam architecture. Therefore, FEM must be implemented in an efficient, compact and cost-effective manner, and is preferably simple to control and monitor.
This paper introduces the design, implementation and verification of the RF front-end module MMIC (single-chip microwave integrated circuit) in the 28GHz 5G communication band (27.5 to 28.35GHz) that meets all the above requirements. The RF front-end was developed by Plextek RFI and implemented using WIN Semiconductors' PE-15 4V voltage, 0.15μm, and enhanced GaAs PHEMT process. It is available in a compact, low cost, SMT (Surface Mount) compatible 5mm x 5mm overmolded QFN package for high volume, low cost manufacturing. It covers 27 to 29 GHz and therefore supports the full 28 GHz 5G band.
1. Design goal
The design of the FEM transmit channel focuses on achieving high efficiency under power retraction to provide linear amplification, which is a requirement of 5G communication systems. The target power added efficiency (PAE) under power backoff is set at 6%, and the third order intermodulation (IMD3) is below -35 dBc (power backoff value: approximately 7 dB from the 1 dB compression point). The RF output power corresponding to the 1 dB compression point (P1dB) is set to 20 dBm. The receive channel needs to achieve a noise figure of less than 4dB (including switching losses) at very low current consumption (maximum 15mA, +4V supply).
The functional block diagram of the RF front-end MMIC is shown in Figure 1. The transmit signal path extends from the left to the right in the upper half of the figure; the input port is on the pin labeled "PA_RFin". The input signal is amplified by a three-stage power amplifier (PA) and then connected to the antenna via an RF power detector and a single pole double throw (SPDT) switch. An on-chip directional power detector monitors the transmitted RF output power and integrates temperature compensation on-chip. The compensated power detector output is determined by the difference between the voltage "Vref" and the voltage "Vdet". A fast switch enable circuit (PA enable circuit in Figure 1) controlled by an (active low) logic signal "PA_ON" is integrated into the chip. The PA can be powered up and down quickly when switching between transmit and receive modes, thereby achieving a current of only 0.1 mA when the PA is not in use, maximizing the efficiency of the overall system.
The PA typically operates at a few dB back from the compression point to keep the modulated signal it emits from being severely distorted. The design method is to optimize the performance of the power amplifier operating at about 7dB back-off at the P1dB point. In order to achieve a better PAE under this operating condition, the PA will be biased in the deep AB class.
2. Design compromise strategy
The design begins with device level simulation of candidate cell transistors. This simulation provides key information such as device size, bias point, target impedance, PA stage, and driver ratio, laying a solid foundation for subsequent fine power amplifier designs.
An important part of this work is to determine how to maximize the PAE under power back-off. In general, this can be achieved by reducing the device's static bias current density. However, the range in which the current density can be down-regulated in this method is limited by the gain and linearity constraints, as both deteriorate as the current density decreases. There is a clear compromise between PAE and gain and linearity under power back-off conditions.
The linearity indicator of primary interest in the design is that under power back conditions, IMD3 must be less than -35dBc. As shown in Figure 2, IMD3 performance is particularly sensitive to fundamental frequency loading conditions with reduced bias current. Figure 2a shows the load-pull simulation results for an 8 × 50 μm device biased to deep AB at 4 V, 75 mA/mm, and the load corresponding to the PAE optimum point at P1 dB is plotted. The figure also shows the performance of IMD3 under the optimal load and power back-off conditions obtained from the simulation, indicating that there is a margin of about 4 dB from the -35 dBc indicator. The simulated PAE is approximately 15% under this power backoff condition, and this efficiency is only factored into the device and does not include any output loss. Figure 2b shows the load corresponding to the P1dB power optimum point and the IMD3 information under the same device and bias operating conditions. It is found that the performance of IMD3 is significantly worse under the same relative power backoff, exceeding the target by more than 5 dB, and the PAE is similar to the former condition, which is about 15.7%.
Figure 2: Impedance point corresponding to the best PAE under P1dB condition and IMD3(a) under the corresponding power back-off condition; impedance point corresponding to the optimal power under P1dB condition and IMD3(b) under the corresponding power back-off condition .
Further evaluation of the performance of the power amplifier under both P1dB and power back-off conditions at other impedance points on the Smith chart. The load conditions in Figure 2a clearly have the best overall performance and are therefore chosen for the output stage design. Finally, a bias current of 52 mA/mm was selected, and an 8x50 μm device was selected as the basic unit of the output stage to meet the power specification requirements. According to the total transmission gain index, it is determined that three-stage amplification is required.
A complete three-stage power amplifier is designed by sequentially selecting the optimum transistor size for the drive amplifier stage and the pre-drive amplifier stage. This also requires careful consideration of design compromises because larger transistor sizes improve overall linearity but reduce PAE. When the size and bias of all transistors are determined, the detailed design of the matching and biasing circuits can be continued. Layout design needs to be considered from the early stages of the design process to avoid introducing excessive parasitic effects and ensuring design achievability. The first and second stages of the amplifier use a common gate bias lead (added on pin PA_Vg12), while the third stage sets a separate bias lead (PA_Vg3). This allows the two voltages to be individually optimized to improve the linearity or PAE of the PA. The drain supply can similarly apply +4V on two separate pins on "PA_Vd12" and "PA_Vd3", although the two pins are connected on the PCB.
The SPDT switch uses a serial-to-parallel structure in which multiple transistors are integrated in the series and parallel branches to improve linearity1. The capacitance of the transistor when it is turned off limits the inherent isolation of the device at high frequencies in the off state. The isolation of the switching transistor is only a few dB2 at 28 GHz. Reducing the transistor size improves the inherent isolation, but increases the insertion loss in the on state and reduces its linearity, so it is not a viable option. The approach taken here is to use on-chip inductor compensation to improve the isolation state of the off state. The careful design ensures low insertion loss in the on-state to achieve high output power of the transmit channel and low noise figure of the receive channel. The switch is controlled by a bit control voltage "Vctrl1", which is set to 4V for the transmit mode and 0V for the receive mode. The "single pole double throw control circuit" (SPDT control circuit) enables single bit control, which is essentially a one-to-two-wire decoder. The total current consumed by the control circuit and the SPDT itself is only 1 mA and is provided by the +4V supply applied at "VD_SW".
The input to the receive channel is located at the "antenna" pin that is connected to the two-stage LNA input via the SPDT. The output of the receive channel is located on the pin labeled "LNA_RFout". Like the PA, the LNA also has a fast switching enable circuit that allows the LNA to consume only as little as 0.1mA when not in operation. The key to the low noise amplifier design process is to find a design that consumes low current, good noise figure, and sufficient linearity.
The important first step is to choose the right transistor size. Multiple short fingers can be used to reduce the gate resistance of the transistor and improve the noise figure. The low-noise two-stage uses series inductive feedback so that the impedance required for the best noise figure is closer to the impedance required for conjugate matching and optimal gain.
The first stage of the low noise amplifier is designed with noise figure as the optimization goal, but still needs to generate enough gain to fully reduce the influence of the second stage noise figure. The noise figure of the second stage of low noise is not important, so this stage is designed to have a higher gain than the first stage. The designed LNA requires only 10 mA of DC current from a +4V supply. The gate bias voltage is applied to pin "LNA_Vg" and the +4V drain bias voltage is applied to "LNA_Vd". The “LNA_Vsense” pin provides monitoring of the bias current. The monitored bias current information can be used to control the gate voltage to compensate for changes in environmental conditions such as temperature. At the correct bias, the voltage at this monitor pin is 3.9V. The process of using enhanced transistors means that only a positive supply voltage is required, making the MMIC very easy to integrate.
Careful electromagnetic simulation is very important to ensure good RF performance of each module. A step-by-step approach was used to add a portion of the circuit to the EM simulation each time, while the rest was still modeled using the model in the Process Design Kit (PDK). Since integrated circuits are used in plastic packages obtained by overmolding processes, compounds injected over integrated circuits also need to be considered in electromagnetic simulation.
3. Evaluation and testing
Figure 3 is a photograph of a radio frequency front end chip. The RF front-end MMIC chip measures 3.38mm × 1.99mm. Its pad/pin location is similar to that shown in the block diagram, and it also integrates multiple ground pads to make it fully RF-ready. It is designed to be packaged in a low cost injection molded 5mm × 5mm QFN package. And considering the influence of the mold plastic, it is necessary to carefully design the RF transition interface from the chip to the PCB. A custom lead frame is designed to achieve this transition, and the RF ports on the package are designed as ground-signal-ground (GSG) interfaces.
After the fabrication and fabrication, the on-chip RF test was performed on multiple chips to confirm that the chip achieved a successful design goal before the package. The RF test results are not given here. All the results given are measured after the chip is fully packaged and mounted on a typical PCB evaluation board.
The PCB evaluation board is designed with low cost laminate materials for high volume production. The packaged RF front-end module samples are assembled onto the PCB evaluation board; all measured performance is calibrated to the package pins on the PCB evaluation board to include the chip-to-PCB transition structure. A TRL calibration unit was designed to calibrate the measured performance to the reference plane of the package. Figure 4 shows a photo of the TRL calibration PCB and a PCB evaluation board.
The RF front-end module MMIC is mounted on the PCB and the verification result is obtained by using the packaged RF pin as a reference surface. A commercially available multi-channel DAC and ADC chip is used to control and monitor the RF front-end module during the verification process. The RF front-end module does not require any negative voltage because it uses an enhanced process. Figure 5 shows a comparison of the measured and simulated S-parameters of a typical RF front-end module's transmit channel. The measured data is in good agreement with the simulation results. In this mode, the LNA is turned off, the SPDT control bit "Vctrl1" is toggled high, and the PA is biased to approximately 70mA total quiescent current at +4V. From 27 to 29 GHz, the small signal gain (S21) is 17.1 dB ± 0.4 dB. The input reflection attenuation (S11) is better than 18 dB over the entire frequency band. Since the output match is the best PAE design under power back-off conditions, rather than the best S22, the S22 (not shown) measured so far is 8 dB or better over the entire frequency band.
The third-order intercept point (OIP3) of the transmit channel referenced by the output is evaluated at a frequency interval of 100 MHz to reflect the wide channel bandwidth in the 5G system. Figure 6 is a graph showing the relationship between the measured OIP3 of a typical RF front-end module and the power at the useful frequency, with power ranging from 1 to 11 dBm. It can be seen that the OIP3 in the 5G frequency band is about +28 dBm, and the change in the useful frequency power in the range of 10 dB is small. The measured and simulated OIP3 vs. frequency is shown in Figure 7, with good consistency.
Although 5G communication systems require linear amplification to maintain modulation fidelity, it is necessary to measure the output P1dB and PAE in order to provide a convenient performance metric. The measured performance is shown in Figure 8. It can be seen that P1dB is around 20.2dBm and rises to 21dBm when saturated. The FEM's transmit channel PAE is about 20%, only slightly lower in the high section of the band.
As mentioned above, the FEM is designed to achieve the best performance metrics (OIP3 and PAE) when the backoff is about 7 dB from P1dB. The specific indicator is that in the dual-frequency test at 100MHz interval, IMD3 (third-order intermodulation term) is -35dBc lower than the required useful signal. This working point is very close to the setting requirements of the 5G system that the RF front end will be used for.
Figure 9 shows a plot of measured and simulated PAE versus total RF output power at -35dBc IMD3 point operation. The measured PAE reached a good 6.5%, mainly because the PA was designed to work in the deep AB class. The total RF output power is approximately 13.5 dBm, which corresponds to an OIP3 power of +28 dBm.
According to the characteristics of the on-chip RF channel power detector, the RF output power can be monitored by a DC voltage. Figure 10 shows the temperature-compensated detector output voltage "Vref-Vdet" (mV in units, logarithmic coordinates) versus output power (in dBm), including a variation range of more than 15dB. This characteristic relationship is linear in logarithmic coordinates, making power monitoring easier.
When using the receive channel of the FEM, the PA is turned off, "Vctrl1" is set to 0V, and the LNA is biased to about 10mA at +4V supply. At this time, 3.9V is observed on the "LNA_Vsense" pin. Figure 11 shows a comparison of measurement and simulation gain and noise figure (NF). The measured small signal gain is approximately 13.5 dB and the gain flatness of the entire frequency band is ±0.3 dB. The receive channel has an excellent noise figure, typically 3.3dB from 27 to 29 GHz, and there is good agreement between the simulated and measured performance.
The receive channel also has fairly good linearity and consumes only a small amount of power (only 40mW: 10mA at 4V). Key indicators such as P1dB and OIP3 are around 6.2 and 21 dBm for the entire frequency band. Figure 12 is a graph showing the relationship between P1dB and OIP3 as a function of frequency.
The RF front-end MMIC described in this article will play a key role in the future 28G band 5G system. The module has been proven to meet all requirements for integration into millimeter-wave phased arrays or beam-switched terminations, and offers superior transmit channel linearity and efficiency, as well as excellent receive noise figure. The key performance indicators of the transmit and receive channels meet the design requirements, making the module ideal for millimeter-wave 5G applications. The chip also includes a variety of useful features such as transmit power detectors, transmit and receive enable circuits, SPDT decoder circuits and receive bias monitoring circuits. It is implemented using the most advanced 0.15μm enhanced gallium arsenide PHEMT process. The module is very easy to control and monitor using common multi-channel ADC and DAC chips. In addition, the module is conveniently packaged in a compact and low cost 5mm × 5mm QFN surface mount plastic package.