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Xilinx XC7Z030-2FFG676i FPGA

The Zynq-7000 series FPGA family is based on Xilinx SOC. Xilinx XC7Z030-2FFG676i also belongs to the same family. The device is available in various speed grades such as -2LI, -3, -1, -1LQ, and -2. The highest speed grade is -3 bears the highest performance. The device of -2LI is operating at programmable logic with VCCBRAM or VCCINT equivalent to 0.95V and is best for use in the applications of low maximum static power. The specifications for speed for both -2 and -2LI are the same. The -1Q and -1LQ speed grade devices are operating at identical speeds and voltages and are best to be used for low power applications. Both AC and DC features of this family of devices are specified for temperature ranges of industrial, commercial, expanded, and extended. Apart from the operational ranges of temperatures and a few other features both AC and DC parameters for electrical and electronic aspects of all speed grade devices are exactly identical. Furthermore, the timing characteristics of industrial and commercial for -1 speed grade devices are also the same. Only a few of the devices are available in industrial, extended, commercial-scale speed grades. The junction temperature along with supply voltage specifications for Xilinx XC7Z030-2FFG676i are representing the worst-case scenarios only. The included parameters are very common in the popular designs of the Zynq-7000 series and are used for dedicated applications only.

DC Characteristics of Xilinx XC7Z030-2FFG676i 

The pressures that are exerted on the device beyond its absolute maximum ratings would cause irreversible damage to the IC if exposed frequently. The stress ratings are based on the datasheet only and its operation at such conditions and beyond these conditions are not implied. The DC characteristics of the device are also applicable to supply banks i.e., VCCO_MIO1 and VCCO_MIO0. The lower power absolute specifications are always applicable to the device. However, the maximum limits of Xilinx XC7Z030-2FFG676i are only applicable for DC signals but not for maximal over and undershoot for AC specifications. The guidelines for soldering and thermal consideration of the device are also specific and must be followed for its operation.

PS Power Sequencing

For Xilinx XC7Z030-2FFG676i the manufacturers have recommended a specific sequence for power ON the device starting with VCCPINT, VCCPLL, and VCCPAUX. After that PS VCCO is supplying power to VCCO_DDR, VCCO_MIO1, and VCC_MIO0 to achieve minimal drawl of current for ensuring the input/output to be in a three-stated power ON state. The input of PS_POR_B is necessary for assertion in GND while power ON sequence is in progress till VCCO_MIO1, VCCPINT, and VCCO_MIO0 to reach at the minimal level of operation for ensuring the eFUSE of PS in integration. Whereas, for the timing of PS_POR_B resets are to be used. The power OFF recommended sequence for the Xilinx XC7Z030-2FFG676i PS supply is in the opposite manner to the power ON sequence. If PS VCCO, VCCPLL, and VCCPAUX are supplying power then identical levels of voltages are required for powering ON the device. The powering ON of VCCPLL is recommended by Xilinx with the supply to which VCCPAUX is powered ON.

PL Power Sequencing

Xilinx has also recommended a dedicated power ON sequencing for Xilinx XC7Z030-2FFG676i PL supply that starts with powering ON of VCCINT followed by VCCAUX, VCCBRAM, VCCAUX_IO and ending at VCCO for achieving minimal drawl of current and ensuring the input/output to be in three-state power ON conditions. The power OFF sequence is supposed to be in the opposite way to the power ON sequence of the device. Now, if VCCBRAM and VCCINT are in the recommended level of voltages then both of these can be ramped and powered ON through the same supply in a simultaneous manner. When voltages of VCCO are greater than 3.3V in its HR input/output bank along its configuration bank 0 then the difference of voltage among VCCAUX and VCCO should not be increasing than 2.625V for more than the power OFF/ON cycle to maintain the reliability of the device.

PL – PS Powering Sequence

Both PL and PS supplies are independent of each other. The PS supplying power through VCCPINT, VCCPLL, VCCPAUX, VCCO_MIO1, VCCO_MIO0, and VCC_DDR before the PL supply is offering any power. Both power regions of PL and PS are independent and isolated for preventing any damage to the Xilinx XC7Z030-2FFG676i device.

Requirements of Power Supply

ICCQ is necessitated by Zynq-7000 devices in order to supply the optimum amount of power at the power ON stage to its configuration. The minimal current requirements must also be met for the device to have its all five supplies in working condition. After meeting current requirements Xilinx XC7Z030-2FFG676i is passing through its power ON reset voltages. The device is supposed to be not configured till VCCINT is applied to it. The power estimator tool of Xilinx must be utilized after the configuration and initialization of the device.

DC Levels (Output and Input)

For the voltages that are recommended values of VIH and VIL are a must. Furthermore, the values of IOH and IOL are also to be guaranteed for operational conditions that are recommended by the manufacturer for Xilinx XC7Z030-2FFG676i at testing points VOL and VOH. However, only specific standards are needed to be tested. All of the conditions are selected for ensuring of specifications to have met. All of the standards are tested at a minimal value of VCCO with its relevant VOH and VOL.

Switching Characteristics of Xilinx XC7Z030-2FFG676i

The standardized specific values for different characteristics of the device such as output and input delay adjustments along three-state delays are described in the high-performance IOB and high range IOB. TIOPI is known as the delay originating from the IOB pad and is going through the input buffer till the I-pin of the IOB pad. The delay is varying and depends on the capacity of the SELECTIO input buffer. Whereas, TIOOP is known as the delay that originates from the pin O and moves through the IOB pad via the output buffer of the IOB pad. This delay is varying and depends on the capacity of the SELECTIO output buffer.