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What Is Xilinx XC6SLX45T-2FGG484i ?

The Xilinx XC6SLX45T-2FGG484i FPGA (Field Programmable Gate Array) device is available in numerous speed grades. The maximum achievable performance is with the -3 variant of the device. Both AC and DC characteristics of the device for its defense-grade and automotive spartan grade are the same as those for the commercially available variant. However, the characteristics of timing for the industrially available variant i.e., -2 speed grade are the same as that used for the commercial-grade device. The speed grades -3Q and -2Q are exclusively retained for the temperature range of expanded mode. The characteristics of timing are equal for all of the devices that have shown for -3 and -2 speed grades for the defense and automotive-grade variants of the device.

The spartan-6 Xilinx XC6SLX45T-2FGG484i FPGA’s have dedicated AC and DC characteristics for its expanded temperature range, industrial, and commercial-scale variants without which it does not work properly. Specific speed grades of the device may be readily available in the market for expanded temperature range or industrial use for both defense and automotive applications.  The mentioned range of supply voltage along with specifications for junction temperature is representing the worst-case scenarios. Most of the designated parameters are common in the typical applications and popular designs of the competitor devices to Xilinx XC6SLX45T-2FGG484i.

Switching Characteristics of Spartan-6 Xilinx XC6SLX45T-2FGG484i

The entire range of values that are represented for Xilinx XC6SLX45T-2FGG484i are grounded on their speed characteristics and variants, for instance, -1, -2, -3N, and -3, etc. The switching characteristics of the device are based on per-speed grade and it could also be designated in production, preliminary, and advanced categories. For the advanced category, the specifications are grounded based on the simulations and are readily available after the specifications of the design are frozen. All of the speed grades of the advance category are considered to be stable enough and conservative. However, there are still chances of minor underreporting. The specifications of the preliminary category are based on engineering sample characterization of silicon. All of the speed grades and devices of the category are intended to give the best indication of expected performance for silicon production. There is a greater chance of the probability for under-reporting delays when compared to the advanced category.

The production category’s specification for Xilinx XC6SLX45T-2FGG484i is released given that there is enough production of silicon in a particular family and its characterization is provided for various production lots. There are no chances of underreporting delays and the customers are receiving a formal email notification in case if changes are made to the device. Conventionally, the slower speed grade of devices is transitioning to production before its faster speed grades are in the market. The entire specifications are representatives for its worst-case supply voltage and its conditions for junction temperature. The -1L speed grade is referring to the lowest possible speed that can be achieved by spartan-6 devices and the -3N speed grade is referring to the highest possible speed that can be achieved by the device family.

The Measurements of Output Delay

The delay in the output of the device is measured through the utilization of Tektronix P6245 probe throughout 4″ of the FR4 trace of microstrip. For all of the testing, standard termination is utilized. For the 4″ trace its propagation delay is separately characterized and then subtracted from the finalized measurement. This is how it is included in the generic testing setups of the device. The testing and measurement conditions for the Xilinx XC6SLX45T-2FGG484i are all reflected in IBIS models with an exception for speed grades in which IBIS format is precluding it.

Different parameters like VMEAS, CREF, RREF, and VREF are all fully describing the testing conditions for every input/output standard.  With the help of IBIS simulation, propagation delay can be predicted accurately within any application. The method comprises few steps such as simulation of the output driver of choice into that of a generic test setup. Recording the values for VMEAS. Simulation of the output driver into a real trace of PCB and then loading it through the use of an appropriate IBIS model for the representation of load. Recording the time for reaching VMEAS. Comparing the results and noticing the decrease or increase in delay that yields to the actual propagation delay of the trace of PCB.

Simultaneous Switching Outputs of Xilinx XC6SLX45T-2FGG484i

Because of the electrical parasitic nature of the device, the given package is only supporting a smaller number of switching outputs at times when using high-drive and fast outputs. The guidelines of Xilinx XC6SLX45T-2FGG484i are describing the maximum possible users at input/output pins for an output signal standard that could be simultaneously switched in a similar direction and maintaining safe switching level noise for the specific signal standard. When the guidelines are met for mentioned conditions is ensuring that the FPGA is operating within a bearable range of adverse effects of power bounce and GND. For every device combination, guidelines are categorized based on output drive current, slew rate, and style of package. The SSO number is also specified with the help of its input/output bank. Multiplying the appropriate numbers from every table for calculation of the maximum possible SSOs that are allowed within the input/output bank.

The guidelines of Xilinx XC6SLX45T-2FGG484i are assuming all pins of the device within bank utilization for the same input/output standard. Generally speaking, lower DRIVE settings are resultant in the improvement of SSO characteristics. However, in some cases, higher DRIVE settings are also improving SSO values as these are improving the noise margin. The analysis through the use of the PlanAhead tool is also supporting mixed standards throughout the bank device. While exceeding the guidelines of SSO may be resulting in an increased GND bounce or power. The resultant effect will degrade the integrity of the signal or will increase the jitter of the system. The SSO recommended values are assuming the FPGA to be soldered on PCB and its board is utilizing standard design practices. Because of the additional inductance of the socket, SSO values are not complying with the Xilinx XC6SLX45T-2FGG484i FPGAs mounted on certain sockets. The powering ON of SSO is assumed to be at 3.3V and setting eh VCCAUX to a value of 2.5V is delivering better characteristics of SSO.