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Xilinx XC6SLX16-3CSG324i Parts

Xilinx XC6SLX16-3CSG324i belongs to the spartan-6 family of FPGAs responsible for delivering capabilities of system integration with lower costs. The family is having a total of 13-member devices. The densities of devices range from 3840 up to 147,443 logical cells. These devices consume much less power compared to their previous competitors. These devices are manufactured on 45nm process technology delivering optimum balance in terms of performance, power consumption, and cost. This family is offering an efficient lookup table with 6 inputs and dual registers enabled along with rich choices for system-level blocks.

Main Features of Xilinx XC6SLX16-3CSG324i

The spartan-6 family is capable of logical optimization, serial connectivity with higher speeds, low-cost design, built-in various system-level blocks, improved input/output standards selection, lower dynamic and static power, staggering pads, zero powered hibernate mode, suspend mode maintaining configuration with enabled wake-up pins, and data transfer rates up to 1080 Mb per second. Furthermore, the devices have compliance for hot-swap, memory interfaces for SSTL, and HSTL, changeable input/output slew rates for improving the integrity of signals, interfaces for Aurora, XAUI, GPON, DisplayPort, serial ATA, CPRI, PCI express, and OBSAI. Xilinx XC6SLX16-3CSG324i devices have enhanced capacity for logic with large logical resources, support for distributed RAM, byte mode writable block RAM, dual flip-flops enabled lookup tables, flexible clocking, lower jitter clocking with phase-lock loops, clock management tiles, and digital clock managers.

Clock Management

The management of the clock in each Spartan-6 Xilinx XC6SLX16-3CSG324i FGPA is capable of having 6 of the CMTs out of which every CMT is having 1 phase-lock loop and 2 DCMs that are to be utilized on a cascaded or individual basis.

Frequency Synthesis in Xilinx XC6SLX16-3CSG324i

The frequency synthesis of this device is independent of the functionality of DCM and its CLKFX180 and CLKFX are to be programmed in a way to enable the generation of the frequency at the output that is equivalent to the input frequency of the DCM when multiplied by a factor M and at the same time divide through factor D. here, M is the integer in the range of 2 till 32 and D is an integer in the range of 1 till 32.

Phase Shifting

The entire nine outputs of CLK i.e., CLKFX180, CLK0, CLKFX, CLK90, CLKDV, CLK180, CLK2X180, CLK270, and CLK2X at the instance when CLK0 is having a connection with CLKFB, can get a shift with the same value that is defined through an integer multiple factors of fixed delay. Therefore, the fixed delay value of DCM could be established through configuration and can also be decremented or incremented dynamically.

Clocking of the Spread-Spectrum

The DCM is capable of accepting and tracking the traditional spread-spectrum inputs of the clock that are given that these are abiding by the clock inputs specification that is recommended for the device Xilinx XC6SLX16-3CSG324i. This device is capable of generating a spread-spectrum source of the clock from that of a standard fixed-frequency oscillator.

Phase-Lock Loop

The phase-lock loop of the Xilinx XC6SLX16-3CSG324i could serve in the form of a frequency synthesizer for a broad frequency range and in the form of a jitter filter for all of the clocks that are in incoming projection along the DCMs. The phase-lock loop’s heart is a voltage-controlled oscillator or VCO having a range of frequency of 400 to 1080Mhz, making it span over an octave. Three distinct sets of the programmable frequency dividers i.e., O, M, and D can adapt to the VCO for fulfilling the requirements of a specific application. D is the pre-divider that is programmable by its configuration reducing the input frequency and feeding on of the inputs of the conventional phase-lock loop phase comparator. The feedback divider is also programmable by its configuration and is acting as a simple multiplier as it is dividing the output frequency of VCO in its frequency range. VCO is having a total of eight outputs that are equally spaced by 45 degrees. Any of these could be selected for driving either of the 6 dividers at the output.

Distribution of Clock in Xilinx XC6SLX16-3CSG324i

Every of the Xilinx XC6SLX16-3CSG324i FPGA is having sufficient clock lines for addressing the variety of the clocking requirements of low skew, higher fanout, and small propagation delay.

Global Clock Lines

The Xilinx XC6SLX16-3CSG324i devices are having a total of 16 of the global clock lines that are having the highest fanout and are reaching each of the clocks of flip-flops. The global clock lines are to be driven through buffers of the global clocks, that are capable of performing glitch-free multiplexing of clocks and clock enabling. The global clocks can also be driven through CMTs that are eliminating the requirement of clock distribution delay.

Block for Memory control

The spartan-6 family of FPGA devices is comprising of a dedicated controller for memory blocks out of which every block is targeting the DRAM which is a single chip and is supporting access for data rates of around 800Mb/s. This memory block controller is having dedicated routing for the inputs/outputs that are predefined. In case, if the memory block controller is not utilized, then the inputs/outputs are available for generic purposes. The memory block controller is offering a broad arbitrated interface that has multi-ports for its logic. In Xilinx XC6SLX16-3CSG324i all of the commands can be communicated and the data can also be pulled and pushed from sovereign integrated FIFOs through the utilization of conventional control signals of FIFO.

PCI Endpoint Block

There is a dedicated PCI endpoint block in spartan-6 Xilinx XC6SLX16-3CSG324i. The PCI Express standard is a point-to-point and packet-based serial interface standard. The transmission of differential signals is utilizing the use of an embedded clock that is eliminating the clock-to-data skew issues of conventional busses that are wide-parallel. The specification of the PCI express base is defining the bit rate to be approximately 2.5Gb/s through each lane in every direction for both reception and transmission. Whenever 8B/10B encoding is utilized, it is supporting the data rate of around 2.0Gb/s through each lane. The LXT devices of the Xilinx XC6SLX16-3CSG324i are encompassing a built-in endpoint block for its PCI express technology that is having compliance with the PCI.