Skip to content

Xilinx XC9572XL-7PCG44I Technical Details

The Xilinx XC9572XL-7PCG44I is from the CPLD family of 3.3 volts which is dedicated to be used for applications where higher performance, higher efficiency, and lower voltage is required such as in the fields of leading-edge fields of computing and communication system. In such systems, lower dissipation of power and higher reliability of devices is of great importance. In-system programming along with IEEE standard 1149.1 boundary scan is supported by the Xilinx XC9572XL-7PCG44I which allows superior capability of design iteration and debugging ability maintaining the device with a minor form-factor packages. This device is capable to work with other platforms too apart from Xilinx such as Spartan-XL, and Virtex etc. which allows the designers of the system to have logical partition among the higher density logic of general purpose and circuitry of fast interference.

The density for logic of Xilinx XC9572XL-7PCG44I device has a range from 800 up to 6400 usable gates along with 36 up to 288 registers. The family of this device is completely pin compatible and is allowing an easy migration of design throughout numerous options of density in a given footprint package. The architectural features of the device are addressing almost all of requirements of the in-system programming. Furthermore, the enhanced capability of pin-locking is avoiding its costly rework of its board. The in-system programming capability of the device throughout the entire range of its operation along with higher rating of programming endurance is offering reconfigurations that are worry-free for the upgrades of system fields. The device’s data retention for a longer time is supporting its system’s reliable and extended operational life. The system’s advanced features are comprising of control rate of output slew along with ground pin which are user programmable for assisting in reduction of noise of the system. Every user pin can be configured with any 2.5 volts, 3.3 volts, and 5 volts. Whereas, the input pins may be configured with either 2.5 volts or 3.3 volts. This device is exhibiting a full 3.3 volts symmetric voltage swing for allowing a balanced fall and rise times.

Description of Architecture

Every Xilinx XC9572XL-7PCG44I device is actually a sub-system which is consisting of various functional blocks along with its input/output blocks that are entirely interconnected through a Fast Connect II matrix switch. The input and output blocks are providing buffer region for outputs and inputs of device. Whereas, every functional block is delivering the capability of programming logic along with additional 18 outputs and 54 inputs. The fast connect II matrix switch is connecting all of the output and input signals of functional blocks to that of the input signals of the inputs of functional block. For every functional block, there are almost 18 outputs which are depending on the pin-count package and is also associated directly with the enable signal of output drive to its input and output blocks.

Functional Block

The functional blocks are comprising of 18 macro cells which are independent of each other and have capability to be configured either as registered or combinational function. The functional block is also receiving reset & set signals, output enable, and global clock. It is also generating 18 outputs which are driving the fast connect II matrix switch. All of these 18 outputs and its counterpart signals of output enable are driving the input and output block as well. The functional block’s logic is implemented in the form of sum of products. 54 of the inputs are offering 108 compliment and true signals to the AND array which is programmable forming a total of 90 product terms. The product term allocator can allocate almost 90 of the available product terms to every macro cell.


The following are the main features of XC9572XL-7PCG44I.

  1. This device is optimized for 3.3 volts higher performance system.
  2. With 5 nano seconds delay (pin to pin) along its internal frequency till 208 M Hz.
  3. The availability is for all packages and is lead free.
  4. The operation is possible on lower power.
  5. It has input/output pins which are 5 volts tolerant and are accepting signals of 2.5 volts, 3.3 volts, and 5 volts.
  6. It has capability of 2.5 volts and 3.3 volts.
  7. The advanced system features are as follows.
  8. The device is in system programmable.
  9. Through fast connect II matrix switch it has fast routing and pin locking ability.
  10. It has 54 input functional blocks.
  11. It has capability of individual allocation of product terms along with 90 regular allocation of product terms with every macro cell.
  12. It is capable of local clock inversion along 1 product and 3 global term clocks.
  13. All pins of user input and boundary pins are having input hysteresis.
  14. It has capability of supporting hot plugging.
  15. It supports IEEE 1149.1 standard for boundary can for all connectable devices.
  16. The device has 4 pin compatibility densities i.e., for 36 up to 288 macro cells along 800 to 6400 utilizable gates.
  17. It is capable of rapid programming in concurrent mode.
  18. It supports efficient and enhanced features of data security.
  19. The device has outstanding reliability and quality. It has up to 10 thousand program and erase cycle rating and data retention ability is up to 20 years.