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Xilinx XC7Z045-2FFG900i In Stock

The Xilinx XC7Z045-2FFG900i is an IC available in -1, -2LI, -2, -1LQ, and -3 grades of speed. The highest possible performance is achieved through -3 grade. The -2LI grade IC is operating on programmable logic of VCCINT/VCCBRAM equal to 0.95V. This IC is separated for lower maximum static power. However, the specification of speed for -2LI devices is the same as that for -2 grade IC. Both devices are utilized for lower power. The AC and DC characteristics of the device have been specified through expanded temperature ranges, industrial, and commercial extended ranges. Apart from the range of temperature for its operation, all of the AC and DC parameters are the same for all speed grades of the device. But, specific speed grade devices are available for industrial temperature ranges, extended and commercial applications. All of the temperatures at the junction point and supply voltage specifications are illustrating the worst-case conditions.

DC Characteristics of Xilinx XC7Z045-2FFG900i

If any stress is applied beyond the absolute maximum ratings may result in permanent damage to the device. The exposure of the device to the absolute maximum rating for a longer period of time will result in the inefficient performance of the device and result in irreversible damage. Therefore, the device must be operated under given conditions for getting better efficiency.

Conditions of Operation

The entire voltage range of Xilinx XC7Z045-2FFG900i is relative to a ground position. Both PS and PL are also common to GND. The core of the processor is operating at 1GHz. The DDR interface is operating at 1333 megabits per second. Whereas the minimum VCCPINT is at 0.97V and the maximum VCCPINT is at 1.03V. It must be noted that VCCBRAM and VCCINT should have a connection to the same point of power supply. The data of configuration is retained even in cases if the VCCO has dropped to 0V. The device is catering VCCO of 3.3V, 2.5V, 1.8V, 1.5V, 1.35V, and 1.2V at ±5%. The current ratings for PL and PS must not exceed beyond 200mA. For the use of encryption of bitstream, VCCBATT is required. In case if there is not battery utilization, then it should be connected to VCCAUX or GND. For the device, to operate in lower power consuming state, its VMGTAVCC must be 1.0V ±3% throughout the entire range of CPLL frequency.  

Quiescent Current

The typical values of Xilinx XC7Z045-2FFG900i are given at a certain nominal voltage at a junction temperature of 85oC along with single-ended resources of SELECTIO. Distinct values for devices that are blank configured having no output load currents, there is no need for active pull-up resistors at the input. Furthermore, all of the input/output pins are in floating and 3-state. Xilinx power estimator tools are utilized for the estimation of static consumption of power for all conditions that are not specified.

PS Power Sequencing

For PS, the sequence which is recommended for powering ON Xilinx XC7Z045-2FFG900i is VCCPINT followed by VCCPAUX and then VCCPPLL. After that VCCO of PS power is supplied for achieving minimal current drawing and ensuring the input/output at 3 states when POWERON. The input at PS_POR_B is necessitated for insertion to GND while powering ON sequence is proceeded till VCCPINT, VCC_MIO0, VCCPAUX reaches to the minimal level of operation for ensuring eFUSE of PS integrity. The power-off sequence that is recommended for Xilinx XC7Z045-2FFG900i is in reverse to that required for powering ON the device. Now, in case if both supplied i.e., VCCPLL and VCCPAUX are having exactly the same voltage levels that are recommended, then both of these could be given power through the same supply and will be able to ramp simultaneously. Xilinx is recommending powering ON both VCCPLL and VCCPAUX with the same power supply keeping an option of ferrite bead filter. Any of the conditions mentioned must be fulfilled at powering OFF stage before the VCCPINT is reaching to 0.80V such as the input of PS_POR_B inserts to GND, input to PS_CLK reference clock is disabled, and VCCPAUX is lesser than 0.70V. These conditions are must to be maintained for ensuring the integrity of eFUSE till VCCPINT has reached the value of 0.40V. The voltage difference in between VCCPAUX and VCC_MIO1 should not exceed beyond 2.625V for every cycle of powering the device ON and OFF for maintenance of its reliability.

PL Power Sequencing

For Xilinx XC7Z045-2FFG900i the powering ON sequence for PL is to start from VCCINT followed by VCCBRAM then VCCAUX, VCCAUX_IO, ending at VCCO for achieving minimal current drawing to make sure that its inputs/outputs are in 3-state powered ON. Whereas, it is recommended powering OFF sequence is exactly opposite to power ON. When VCCBRAM and VCCINT are having the same level of voltages then both may be provided with the same power supply at the same time. When VCCO, VCCAUX, and VCCAUX_IO are having the same level of voltages that are recommended then these can be ramped and given the same supply simultaneously. The difference of voltage in between VCCAUX and VCCO should not exceed beyond 2.625V for every powering ON and OFF cycle for maintenance of reliability of Xilinx XC7Z045-2FFG900i. For achieving minimal drawl of current during power ON sequence for transceivers GTX then VCCINT should be initialized first, followed by VMGTAVCC, then VCCINT, and VMGTAVTT. In case, if these sequences are not maintained then a higher current may be drawn during the cycle of power ON and OFF.

AC Switching Characteristics

The AC switching characteristics of Xilinx XC7Z045-2FFG900i are specified according to the speed grade of the device. The switching characteristics may be divided into categories such as production, preliminary, and advance. The advanced specifications are grounded on the simulations only and are available whenever the device specification for design is frozen. The speed grades of the device designations are assumed stable, but still certain underreporting is reported.

Testing of AC Switching Characteristics

The internal parameters of timing for Xilinx XC7Z045-2FFG900i have been derived through the measurement of internal patterns after testing. The AC switching characteristics are representing the worst possible case for junction temperature and supply voltages. Specifically, precise and worst-case data utilization of values is reported through an analyzer of static timing that back annotate the netlist of simulation.