Xilinx XC7Z035-2FFG676i belongs to the Zynq-7000 family of FPGA. The architecture of the device is based on Xilinx SoC. This family of FPGA devices are integrating several features. The device is available in both double and single-core depending on the application for which it is used. The device is grounded on Xilinx’s programmable logic or PS of 28nm. The device has an outstanding ARM Cortex A-9 processor that is considered the core of the device. Furthermore, these devices are having integrated on-chip memory, interfaces for peripheral connectivity, and external memory too.
Description of Processor
The processor of the Xilinx XC7Z035-2FFG676i is having four major blocks comprising the interconnects, input/output peripherals or IOP, memory interfaces, and the application processing unit or APU.
Application Processing Unit
The application processing unit of Xilinx XC7Z035-2FFG676i has several features such as it has single or dual-core ARM Cortex A-9 MP Cores. The ARM Cortex A-9 features comprise 2.5 DMIPS per MHz. The operational frequency range of the processor range from 667Mhz to 866Mhz for wire bond mode and flip-chip mode, it ranges from 667Mhz up to 1GHz. The APU has the capability of operating in a single processor, has dual modes for the asymmetric processor, and dual symmetric processor. The APU also has double and single precision floating points up to 2.0 MELOPS per MHz. There is a media engine known as NEON for the support of SIMD. The APU has support for the compression of code with its thumb-2. The level-1 caches are supporting separate data and instruction up to 32Kb each. The application processing unit is a four-way set associative. There is a built-in memory management unit, secure mode operation is handled with TrustZone. There is an eight-channeled DMA. The APU has support for multiple transfer types i.e., scatter-gather, peripheral to memory, memory to peripheral, and memory to memory.
Timers and Interrupts of Xilinx XC7Z035-2FFG676i
There are various timers and interrupts in the Zynq-7000 series of FPGA. The cross-trigger interface enables the triggers and breakpoints of hardware. There is trace support and CoreSight debug for Cortex A-9. For tracing and instruction, there is a program trace macro-cell. There are 2 triple counters and timers along 3 watchdog timers and a controller for general interrupt.
The Xilinx XC7Z035-2FFG676i unit of memory interface comprises a controller for dynamic memory and an interface module for controlling static memory. The purpose of a dynamic memory controller is to extend support for DDR memories. The controller for static memory is extending support for interfaces of NAND flash, interface for NOR flash, parallel data bus, and an interface for Quad-SPI flash.
Dynamic Memory Interfaces of Xilinx XC7Z035-2FFG676i
The controller for DDR memory is multi-protocol and is being able to be configured for delivering wide access in 32 or 16 bits up to 1GB address space through the utilization of a unity rank configuration of 32, 8, or 16-bit memories of DRAM. There is dedicated 16-bit bus-access for the ECC support. The PS is incorporating associated PHY and controller for DDR comprising of its dedicated inputs/outputs. The speed support is up to 1333Mb/s for its DDR3 memory. The controller of the DDR memory is having the capability of multi-port and is enabling the system of processing a programmable logic in common access for shared memory. There is a total of 4 slave ports for the purpose to serve one as a 64-bit port that has dedicated use for the processor through the controller of level-2 cache and is configured for lower latency. For PL access, there are dedicated ports of 64-bit. There is a single 64-bit AXI-port that is common to all of the masters of AXI ports through a central interconnect.
Static Memory Interfaces of Xilinx XC7Z035-2FFG676i
The static memory interfaces of the Xilinx XC7Z035-2FFG676i are having support for external static memories as well. There is a data bus of 8-bit SRAM that can extend support to 64Mb. There is a NOR flash of 8-bit supporting till 64Mb.
There is a multi-layered interconnect in Xilinx XC7Z035-2FFG676i which is responsible for connecting IOP, interface unit of memory, APU, and PL. This interconnects supporting numerous master-slave transactions simultaneously and is non-blocking. The interconnect is fashioned in a way that it has latency for masters e.g., the master of ARM CPU is having displacement paths to reach memory and the masters that are bandwidth critical like PL masters are having higher throughput connection for slaves along the way they require to communicate. The regulation of traffic can be easily made through interconnecting with its QoS block. The QoS is featuring the regulation of traffic generated through CPU and DMA controllers.
Programmable Logic of Xilinx XC7Z035-2FFG676i
The key features of programmable logic or PL of the device include having a configurable logic block or CLB, 8 lookup tables in every CLB for distributed memory, and random logic implementation. The memory lookup tables are also configurable in two 32-bit block RAM or single 64-bit block RAM. These lookup tables can also be configured in the form of the shift register. There are sixteen flip-flops through every CLB. There are two 4-bit adders in the cascaded mode for featuring arithmetic functions. The block RAM is of 36Kb.
2 JTAG ports could be combined or utilized individually. Whenever combined, a single port is utilized for the ARM Cortex A-9 processor downloading of code and for the operations of run-time, PL debugs PL configuration and logic analyzer that is pro-embedded. This is enabling apparatuses like the software development kit of Xilinx and ChipScope Pro Analyzer for sharing a sole cable for downloading from the Xilinx database. Whenever JTAG ports are split, one of its ports is utilized for support of PS encompassing direct entree to the interface of ARM DAP. This interface of CoreSight is enabling the utilization of ARM acquiescent to correct and its software development tools like development studio 5. Other of the JTAG ports could be utilized by tools of Xilinx FPGA for accessing PL encompassing the downloads of bitstream configuration and PL debug along with the analyzer for integrated logic. This is the mode where workers could download and correct the PL in the form of separate FPGA.