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Xilinx XC7A35T-2FGG484i Chip

The Xilinx XC7A35T-2FGG484i is a device of Xilinx-7 series FPGA. The device is comprising of 4 families that address detailed system requirement range that encompass inexpensive, minor form facto, higher volume applications, logical capacity, and capabilities of signal processing. The family of the device is consisting of the spartan-7 family that is inexpensive, has lower power consumption, and has high input/output performance. These devices are available in small form factor packages for the smallest footprint of PCB and are low cost too. The Artix-7 family is ideal for lower power-consuming applications and has requirements for logical throughput, higher-end DSP, and serial transceivers. These devices are also delivering a lower bill of materials for cost-sensitive applications. The Kintex-7 family of Xilinx XC7A35T-2FGG484i bears the best performance with double improvements when compared to its older generations and enables a novel class of FPGA. The Virtex-7 family is best suited for getting double improvement in the system’s performance.

The Xilinx XC7A35T-2FGG484i devices are designed based on state-of-the-art lower power consumption, and higher performance delivering technology with 28nm of higher-k metal gate processing technology. The device has unparallel performance capabilities along 2.9Tb/s of input/output bandwidth, cell capacity of 2 million, and 5.3 TMAC/s per DSP. The device is consuming almost 50 percent of lesser power than its previous generations and offers a fully programmed alternative for ASICs and ASSPs.

Features of Xilinx XC7A35T-2FGG484i

The device is based on advanced higher performance logic and has 6 input lookup tables configurable in the form of distributed memory. It has a block ram of 36Kb having FIFO logic for data buffering. The device has higher speed serial connectivity along an integrated multi-gigabit transceiver having a range starting from 600 Mb/s and can reach up to 6.6 Gb/s with a special lower power mode and optimized interfaces. The Xilinx XC7A35T-2FGG484i has DSP slices having 25×18 multipliers, a pre-adder, and a 48-bit accumulator for the best performance of filtering. This IC also has a clock manager of mixed-mode, phase-locked loops, and clock management tiles for offering lower jitter and higher precision. The configuration options are wide in the device comprising of commodity memories support, AES encryption up to 256 bits, and an integrated SEU correction and detection mechanism.

SSI Technology

The stacked silicon interconnects technology brings numerous challenges with the creation of higher capacity FPGAs such as Xilinx XC7A35T-2FGG484i. The SSI technology is enabling numerous super logic regions that are to be combined over an interposed layer through the utilization of an established assembly and manufacturing techniques from leaders of industry for the creation of single FPGA with over 10 thousand SLR connections, delivering ultra-high connectivity in terms of bandwidth and lower latency and lower power consumption. The SSI technology is enabling to produce good quality FPGAs rather than producing conventional FPGAs bearing highest performing devices.

Configurable Logic Blocks

The configurable logic blocks of the Xilinx XC7A35T-2FGG484i comprise of real six input lookup tables. The lookup tables are having memory capabilities with a shift register and register functionalities. The lookup table of these FPGAs is could be configured in the form of a six-input lookup table too as 64-bit ROM along with single output or two five-input lookup tables with separate outputs but common address logic. Every lookup table can also be registered in the form of a flip-flop. A configurable logic block is formed after combining lookup tables, its eight flip-flops, multiplexers, and arithmetic carry logic from a single or two slices. Any four flip-flops can also be configured as latches.

Clock management

The key features of the architecture of Xilinx XC7A35T-2FGG484i clock management comprise of higher speed buffers and its routing mechanisms for lower skew clock distribution. This also includes the phase-shifting and frequency synthesis along with jitter filtering, and clock generation for lower jitter. The device has around 24 of clock management tiles out of which each has a phase-locked loop and mixed-mode clock manager.

Distribution of Clock

The Xilinx XC7A35T-2FGG484i has 6 different kinds of clock lines such as higher performance clock, BUFMR, BUFH, BUFIO, BUFR, and BUFG for addressing various requirements of clocking like lower skew, small propagation delay, and higher fanout, etc.

Block RAM

A few of the key characteristics of block RAM of Xilinx XC7A35T-2FGG484i are dual-port block RAM of 36Kb with port widths of 72. The block RAM has a programmable FIFO controller and integrated circuitry for optional error correction. Every device is having around 5 up to 1880 dual-port blocked RAMs out of which every port has a storage capacity of 36Kb.

Synchronous Operation

The clock is utilized for controlling every memory access either to read or write. The entire write enables, clock enables, addresses, data, and inputs are all registered. No function is performed without the intervention of a clock. The clock is fed to the input address and all of the data is retained till the next operation. There is a discretionary register for an output data pipeline that is allowing higher clock rates at additional latency of clock cycles. While the write option is in use, output data is reflecting in the form of data stored previously or the latest written data. However, it can also remain unchanged.

FIFO Controller

The integrated FIFO controller in Xilinx XC7A35T-2FGG484i for synchronous and asynchronous multi-rate operation is incrementing the internal addresses and is delivering a four-way handshake i.e., almost empty, almost full, empty, and full. The flags of almost empty and almost full can be programmed freely. The depth and width of the FIFO controller can be programmed freely like block RAM; however, ports of reading and writing are having the same width.

Phased Lock Loop and Mixed-Mode Clock Manager

Both phased lock loop and mixed-mode clock manager are sharing alike features. Both of these can serve in the form of a frequency synthesizer for a broader frequency range and in the form of a jitter filter for all incoming clocks. The centric point of both components is having a voltage-controlled oscillator that is increasing or decreasing the voltage that is received from the phase frequency detector. Three different types of frequency dividers are there i.e., O, M, and D. D is a pre-divider that is reducing the frequency at the input and is feeding single input of conventional phase lock loops’ frequency or phase comparator. M is a feedback divider that behaves like a multiplier as it is dividing the output frequency of the voltage-controlled oscillator before it is fed to the phase comparator’s inputs. Therefore, the values of M and D must be specified appropriately for keeping the voltage-controlled oscillator within its range.