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What is Xilinx XC6SLX45T-3CSG324i ?

The Xilinx XC6SLX45T-3CSG324i device belongs to the Spartan-6 family delivering capabilities of system integration along with the lowest costs and supports a large number of applications. The spartan-6 family consists of a total of 13 devices having densities expanded in the range of 3840 till 147443 logic cells and consumes less power when compared to the previous family of similar devices. This device has fast and broad connectivity capabilities. This IC is grounded on the 45nm of lower power consumption technology delivering optimum balance in terms of performance, power, and cost and is offering an efficient dual register enabled lookup table having 6 inputs with a built-in system for a rich selection of different blocks. The blocks are comprising of 18 Kb of blocked rams divided into 2 parts of 9 Kb each.

The device also has 2nd generation DSP slices of DSP48A1, memory controllers of SDRAM, efficient blocks for clock management in mixed-mode, highly optimized power serial transceivers, power management modes, configuration options with auto-detection mode, DNA protection of the device, and efficient IP security enabled with AES. The Xilinx XC6SLX45T-3CSG324i Spartan-6 FPGA has to offer a better solution in terms of higher volume logical design, embedded applications that are cost-sensitive, and DSP design of consumer’s choice. The design of the device is in a way that offers flexibility and effective ways for the designers to focus on innovation by integrating the software and hardware together achieving a specific goal.

Features of Xilinx XC6SLX45T-3CSG324i

Belonging to the Spartan-6 family, the IC has numerous features such as logic optimization, serial connectivity with higher speeds, low-cost design, different blocks integrated together, efficient selection for input/output standards, staggering pads, lower dynamic and static power, and the large quantity of plastic wire-bonded packages. Xilinx XC6SLX45T-3CSG324i has a dedicated mode for hibernation for power down consuming zero power, with suspension mode it maintains the current state and its configurations along with multi-pin wake-up and control enhancement. The device is available in different speed grades like -2, -3, and -3N. The data transferring capabilities of the device is up to 1080 Mb/sec through each differential input/output, the output drive is selectable up to 24mA through each pin. The device has hot-swapped compliance too. It has adjustable slew rates for improving the integrity of signals.

The higher speed interfaces are comprising of XAUI, DisplayPort, GPON, EPON, CPRI, OBSAI, PCI, IG ethernet, Aurora, and serial ATA. The device is enabled with higher performance signal and arithmetic processing. It has to cascade and pipelining capabilities along with integrated memory controller blocks. Xilinx XC6SLX45T-3CSG324i supports data rates up to 800 Mb/sec with a distributed RAM support and an optional shift register. The block ram of the device has a vast granularity range. The digital clock managers of the device are eliminating distortion in duty cycle and clock skew. The phase-locked loops are for lower jitter clocking.


The Xilinx XC6SLX45T-3CSG324i spartan-6 FPGA can store configuration in customized data form in the internal latches of SRAM type. The configuration bits are in the range of 3MB to 33MB that depends on the size of the device and implementation options of the user design. The storage of configuration is volatile and is to be reloaded when FPGA is powered up. The configuration is to be reloaded whenever the device is powered OFF and then powered ON. Storage can be reloaded by pulling PROGRAM_B pin to LOW. There are numerous methods available for reloading configuration data. The configurations of bit-serial mode can either be in form of master serial mode in which the FPGA is generating configuration clock signal and its configuration data of external source is also clocking the FPGA.

The configuration information of bitstream in Xilinx XC6SLX45T-3CSG324i is generated through software ISE through a tool known as BitGen. The process of configuration is generally executing the program such that detection of power-up or PROGRAM_B must be in Low, the entire memory configuration is to be cleared, mode pins are sampled for configuration determination in either slave or master mode and parallel or bit-serial mode. The configuration data is to be loaded starting from the detection of bus-width pattern that is followed via synchronization word and checking the proper code of device that is ending through cyclic redundancy check for complete bitstream. The device is intelligent enough to predict which configuration to load next and the time of its loading too. Spartan-6 FPGA Xilinx XC6SLX45T-3CSG324i is comprising of a distinct and DNA identifier that has the purpose of user tracking, IP protection, and anti-cloning of design. The bitstreams of the device are protected using AES encryption.


Most of Xilinx XC6SLX45T-3CSG324i configuration data can be read back without affecting the operation of the system.

Configurable Logic Blocks

In Xilinx XC6SLX45T-3CSG324i every of CLB is consisting of two slices that are arranged side-by-side in the form of vertical columns. A total of three sub-types of CLB slices are there in its architecture i.e., SLICEL, SLICEM, and SLICEX. Every slice is having 4 distinct lookup tables and 8 flip-flops with miscellaneous logic. These lookups are of general-purpose and having support for sequential logic. The synthesis tools of the device are taking an advantage of such highly effective logic, memory, and arithmetic features.

Clock Management

Each of the Xilinx XC6SLX45T-3CSG324i devices is having approximately 6 clock management tools, each of which has two digital clock managers with a single-phase lock loop that could be used in cascaded mode or individually.

Phase Shifting

The CLK0 is in connection with CLKFB while the other 9 outputs of the clock could be shifted through a common count by defining an integer with multiples of fixed delay. Whereas, a fixed value of digital clock management can be settled in configuration and can be decremented and incremented too on a dynamic basis.

Clock Distortion

The device is delivering abundant clock lines for addressing various of requirements of clocking for higher fanout, lower skew, and shorter propagation delay.

Global Clock Lines

In every spartan-6 FPGA, Xilinx XC6SLX45T-3CSG324i is having 16 global clock lines with higher fanout and could reach to the clock of the flip-flop. The global clock lines should be driven through buffers of the global clock that can perform multiplexing of the clock without any glitches enabling function of the clock.