The Xilinx XC6SLX45-2FGG484i is a device that is providing leading capabilities of system integration with lower costs for a higher volume of different applications. This device family is delivering expanded densities that range from 3840 to 147,443 logic cells. The best feature is its less power consumption when compared to previous families. This device has comprehensive and faster connectivity too. The device is manufactured based on the technology of a 45nm lower power copper process that is capable of delivering optimum balance when it comes to performance, power, and cost. This device is offering a novel, dual register lookup of six inputs table along with a vast selection for its built-in blocks on its system level. Such blocks are comprising of 18KB of block RAM with DSP48A1 slices of the second generation, memory controllers (SDRAM), efficient clock management blocks with mixed mode, blocks for higher speed enabled transceiver that is power-optimized, modes for advanced system-level power, options for auto-detected configurations, and efficient IP security along with device DNA and AES protection. Such features are providing a lower cost programmable alternative for custom ASIC products having ease of use. This device is offering an optimum solution for higher volume logic designs, embedded applications that are cost-sensitive, and DSP designs that are consumer-friendly.
Features of Xilinx XC6SLX45-2FGG484i
The device has a lot of features such as logic optimization, higher-speed connectivity in serial mode, lower cost, and availability of various integrated blocks. This device has augmented selection for its input/output standards with staggered pads, packages with higher volume plastic wire, lower dynamic and static power, a mode for hibernating power down for zero power management. The suspended mode is maintaining the configuration and its state along with multi-pin wakeup control enhancements. The higher performance of the device is with 1.2V core voltage in its -2, -3, and -3N grades. The device has interface banks with multi-standards and multi-voltage. It can transfer data up to 1080 Mb/s at its differential input/output. It has a selectable output drive up to 24mA per pin.
The device has hot-swapped compliance with adjustable input/output slew rates for improvement in the integrity of signals. It has memory control blocks such as LPDDR, DDR3, DDR2, and DDR. The supported data rate is up to 800 Megabits per second. It has abundant logic resources and has enhanced logic capability with distributed support of RAM and a discretionary shift register. The block RAM is with a big range of granularity. The Xilinx XC6SLX45-2FGG484i has a feature of fast block RAM with the enabled byte write, clock management tile, flexible clocking, lower noise, digital clock managers for the elimination of clock skew along with distortion of duty cycle. It has lower jitter because of its phase-locked loops. Furthermore, it has pin auto-detection enabled configuration along with efficient security for its protection of design.
The Xilinx XC6SLX45-2FGG484i has an option for its configuration data to be read without any disruption in the operation of the system.
Management of Clock
The Xilinx XC6SLX45-2FGG484i has a total of 6 clock management tiles. Every clock management tile is having one phase lock loop and two digital clock managers that are to be used collectively or individually.
Digital Clock Manager
The digital clock manager is providing 4 phases for the input frequency that are shifted at 900 apart. This is also offering double frequency CLK2X and its CLKDV is offering a slight clock frequency that is aligned to CLK0. There is the possibility of dividing CLKIN by two. There are zero delays in the DCM whenever the signal of the clock is driving CLKIN and the CLK0 output is being fed back to that of input of CLKFB.
Phased Lock Loop
The Xilinx XC6SLX45-2FGG484i has a phased lock loop that serves as a synthesizer of frequency for broad frequency range and in form of a filter for jitter for incoming clocks. There is a voltage-controlled oscillator in PLL which is known as its heart having a range of frequency in between 400MHz to 1080MHz spanning over an octave. 3 sets of programmable frequency dividers can adapt to VCO for any required application. The pre-divider configuration is reducing the input frequency and is feeding input to a traditional PLL comparator for phases. Feedback divider configuration is acting as a multiplier as it is the diving output frequency of VCO earlier than any other input through phase comparator. The outputs of the VCO are equally dispersed by an angle of 45o.
Blocked Random Access Memory
Each Xilinx XC6SLX45-2FGG484i is having around 12 to 268 dual-port blocked RAMs. Every dual port of blocked RAM is having two independent ports that are capable of sharing data storage.
Digital Signal Processing 48A1 Slice
The applications of DSP are using several binary accumulators and multipliers which are implemented in the best possible way through dedicated DSP slices. Xilinx XC6SLX45-2FGG484i has numerous low-powered, fully customized, dedicated DSP slices. Each slice is consisting of an 18×18 bit multiplier of two’s complement along with an accumulator of 48 bits. Both multiplier and accumulator are capable of operating in a range of 390MHz. Furthermore, the DSP slice is offering an extensive speed increment and pipelining capabilities for enhancing efficiency in numerous applications such as input/output register files with memory-mapped, wide bus multiplexers, and dynamic bus shifters.
Manu of the Xilinx XC6SLX45-2FGG484i single-ended outputs are using traditional CMOS push/pull structure at the output that is driving higher towards VCCO and lower towards GND. It may either be considered in a higher Z-state. There are numerous features of the system available for the designer to invoke the input/output in design like differential termination resistors and weak pull-down and pull-up resistors at the internal side.
The transceiver of Xilinx XC6SLX45-2FGG484i
There is a requirement for an ultra-fast transmission of information among ICs through long or short distances. Therefore, it requires a dedicated circuitry on-chip with differential input/output capability of dealing with the integrity of signals at higher data rates. The Xilinx XC6SLX45-2FGG484i device is having a 2 to the 8-gigabit circuit as a transceiver. Every gigabit transceiver port is combined along with receiver and transmitter with capability in operation at different data rates till 3.2 gigabits per second. Both receiver and transmitter are separate circuits utilizing distinct PLLs for multiplication of input frequency given as input through certain numbers among 2 and 25 for becoming bit-serial data clock.