Xilinx XC2C512-10PQ208I ApplicationField
-Wireless Technology
-Cloud Computing
-Internet of Things
-Medical Equipment
-Consumer Electronics
-Industrial Control
-Artificial Intelligence
-5G Technology
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Xilinx XC2C512-10PQ208I FAQ
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Xilinx XC2C512-10PQ208I Features
• Industry’s best 0.18 micron CMOS CPLD
– Fastest in system programming
· Multiple global clocks with phase selection per
· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
– Multi-voltage I/O operation — 1.5V to 3.3V
· Clock divider (divide by 2,4,6,8,10,12,14,16)
· Multiple global output enables
– Advanced design security
macrocell
– Four separate I/O banks
· 1.8V ISP using IEEE 1532 (JTAG) interface
– Optional bus-hold, 3-state or weak pullup on selected I/O pins
– Global signal options with macrocell control
– IEEE1149.1 JTAG Boundary Scan Test
· DataGATE enable signal control
· Global set/reset
– Optional Schmitt-trigger input (per pin)
· Optional DualEDGE triggered registers
– Pb-free available for all packages
– As low as 14 μA quiescent current
• Advanced system features
– Hot Pluggable
– As fast as 7.1 ns pin-to-pin delays
– Unsurpassed low power management
· 100% product term routability across function block
– Optimized architecture for effective logic synthesis
– 208-pin PQFP with 173 user I/O
· CoolCLOCK
· Superior pinout retention
– Open-drain output option for Wired-OR and LED drive
– 256-ball FT (1.0mm) BGA with 212 user I/O
– Optional configurable grounds on unused I/Os
– PLA architecture
• Optimized for 1.8V systems
– RealDigital 100% CMOS product term generation
– Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
– 324-ball FG (1.0mm) BGA with 270 user I/O
• Available in multiple package options
– Flexible clocking modes
Request Xilinx XC2C512-10PQ208I FPGA Quote, Pls Send Email to Sales@raypcb.com Now
Xilinx XC2C512-10PQ208I Overview
Description
The CoolRunner-ll 512-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the lowpower stand-by and dynamic operation, overall system reliability is improved This device consists of thirty two Function Blocks interconnected by a low power Advanced Interconnect Matrix(AlM).
The AlM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-tem PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.
Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds.A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as “direct input”registers to store signals directly from input pins.
Features
· Optimized for 1.8V systems
As fast as 7.1 ns pin-to-pin delays
As low as 14 uA quiescent current
· Industry’s best 0.18 micron CMOS CPLD
Optimized architecture for effective logic synthesis
Multi-voltage /O operation -1.5V to 3.3V
· Available in multiple package options
208-pin PQFP with 173 user I/O
256-ball FT(1.0mm) BGA with 212 user I/O
324-ball FG(1.0mm) BGA with 270 user I/O
Pb-free available for all packages
· Advanced system features
Fastest in system programming
·1.8V ISP using IEEE 1532(JTAG) interface
IEEE1149.1 JTAG Boundary Scan Test
Optional Schmitt-trigger input(per pin)
Unsurpassed low power management DataGATE enable signal control
Four separate /O banks
RealDigital 100% CMOS product term generation
Flexible clocking modes Optional DualEDGE triggered registers Ciock divider(divide by 2,4,6,8,10,12,14,16)
CoolCLOCK
Global signal options with macrocell control
Multiple global clocks with phase selection per macrocell
Multiple global output enables Global set/reset
Advanced design security
PLA architecture
Superior pinout retention
100% product term routability across function block
Open-drain output option for Wired-OR and LED drive
Optional bus-hold,3-state or weak pullup on selected /O pins
Optional configurable grounds on unused /Os
Mixed I/O voltages compatible with 1.5V,1.8V,
2.5V, and 3.3V logic levels
SSTL2-1, SSTL3-1, and HSTL-1/0 compatiblility
· Hot Pluggable
The Xilinx CPLDs (Complex Programmable Logic Devices) series XC2C512-10PQ208I is 512 MACROCELL 1.8V ZERO POWER ISP CPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
Xilinx XC2C512-10PQ208I Tags
1. Xilinx CoolRunner-II CPLD development board
2. Xilinx XC2C512
3. CoolRunner-II CPLD starter kit
4. CoolRunner-II CPLD evaluation kit
5. XC2C512 evaluation board
6. XC2C512-10PQ208I Datasheet PDF
7. XC2C512 development board
8. CoolRunner-II CPLD XC2C512
9. CoolRunner-II CPLD evaluation kit
Xilinx XC2C512-10PQ208I TechnicalAttributes
-Delay Time tpd(1) Max 9.2ns
-Mounting Type Surface Mount
-Package / Case 208-BFQFP
-Number of Logic Elements/Blocks 32
-Operating Temperature -40℃ ~ 85℃ (TA)
-Supplier Device Package 208-PQFP (28×28)
-Programmable Type In System Programmable
-Voltage Supply – Internal 1.7V ~ 1.9V
-Number of I/O 173
-Number of Gates 12000
-Number of Macrocells 512
