It is often necessary to fabricate the semiconductor layers of HFC Laminates and high-frequency substrates in a laboratory. Especially those made of PEDOT: PSS, TPT, or PEDOT: PSS/TPT (if you want to fabricate at a lower frequency), as well as quite different materials used for the device and substrate layers. This blog post gives an overview of fabrication guidelines from the RO4830 standard for these laminates.
First, it is good to study the fabrication training manual for the Semiconductor Processes and Laminates, which is available on the Rayming PCB & Assembly website. This training manual includes information that applies to many of these laminates even though people are not using them yet. It is also good to study the HFC design notes in RO4830. These notes are on memory frequency, leakage current, maximum bias voltage, and other issues that affect device performance.
When you have made all the design decisions and fabricated a few samples, you are ready to know more about fabrication guidelines. RO4830 has several chapters that define fabrication guidelines and process procedures, but an introductory list is above.
The RO4830 standard defines fabrication guidelines for most laminate types used in high-frequency printed circuit boards. The standard also requires a laminate sample sent to Rohm and Haas for fabrication qualification testing. This is to verify that the properties of the laminate fabricator’s production parts meet specified values as closely as possible. Rohm and Haas have developed a qualification procedure. This procedure helps verify that a laminate fabricator’s laminate meets RO4830 standard values. We use it as the basis for the acceptance of a supplier.
We identify the intended use of the laminate in RO4830. It helps to clarify the requirements for each type of laminate. For example, suppose you deposit solid conducting material on both sides. It must have a specified thickness and surface finishing so as not to touch the sides of other layers and shorts out electrical contacts. If we use a conductive surface for high-frequency chip carriers, there may be some limitations on patterns allowed on this surface.
How is the laminate stored influence its performance? First, it is necessary to store. You should keep the samples in a desiccator until they are ready to send for fabrication qualification testing. If you do not keep the laminates appropriately, some may fail the qualification process.
The laminates are typically quite thin. In some cases, they are usually less than 1 mil and less than 250 nm. Therefore, the material handling requirements to handle them without damage are greater than for thicker laminates. It may be necessary to use a vacuum pick-up tool, a clean room with proper glove boxes, or another similar method for transporting the samples from place to place during the fabrication process.
Inner Layer Preparation
We remove the two substrates into an alignment fixture. Then we glue together the substrates on the insulator material, with PEDOT: PSS on the dielectric side and PEDOT: PSS/TPT on the conductive side. Finally, we place the laminates in a vacuum oven at 200°C to cure the epoxy.
The tooling consists of stainless steel or aluminum. As a result, the tooling materials are most susceptible to metal contamination and internal oxidation during laminating. Therefore, verify that the material meets RO4830 requirements when ordering tooling from a fabricator.
2. Surface Preparation for Photoresist Processing and Copper Etching:
We clean the surfaces by wiping them with a detergent wipe. Then the silicon photoresist is spun on the substrate by an air knife. It is contact printed to produce a 0.5-0.8µm thick cross-section of the dielectric used in the laminate. The thickness of this section must be within 0.2% of the laminate’s thickness specification for that type of laminate.
3. Oxide Treatment:
The oxide layer of each substrate is wet etched with a solution of 1:1 HF and H2O2. Select a wet to etch chemistry that will remove the copper but not attack the PEDOT: PSS/TPT.
4. Multi-Layer Bonding:
We realign the photoresist surface, and a new copper surface layer is etched. Then we immerse the copper surfaces in an HF-H2O2 solution to remove oxides from the dielectric. There are two types of bonding between two laminates – through layer, used for chip carriers, and through- via, used for other circuit patterns on high-frequency laminates.
We do the drilling to provide access to adjacent layers. The drill must first penetrate one surface and then exit through the other using an end mill to access the adjacent layer. Normally, we lay out a correctly orientated photoresist pad pattern on the substrate surface that provides alignment for drilling. The drill bit usually consists of cobalt-tungsten carbide (CoWC) material. This material must be free of any oxide contamination when using a 0.
Calculating Spindle Speed And Infeed
We calculate the spindle speed by dividing the end mill’s diameter by the depth of the cut. So, the end mill does not meet any plated through-holes since we make partial cuts in some cases. Therefore, the laminate thickness must be greater than the end mill’s diameter. For example, a 6- and 0.5-layers thick laminate with an end mill diameter of .025 inches would require a spindle speed to cut off about 8,000 RPM. An alternative is to use a smaller diameter and higher spindle speed. For example, a 7- and 0.35-layers thick laminate with an end mill diameter of .020 inches would require a spindle speed to cut about 27,000 RPM.
We feed the cut end mill along the length of the through-hole to produce the laminate’s thickness requirement.
Three major PTH process steps affect the strength of materials used in biomedical applications.
1. Surface Preparation: The PTH process helps clean and remove oxides from the surfaces of the materials. You should perform the process in a cleanroom. The first step is a wet etch to remove any oxides and phosphorous from the material surface, thus exposing bare metal. Next, an HF-H2O2 solution must be applied and annealed to remove any phosphorous that may taint the PTH exposure. Since barium sulfate will float during this step, you must remove it during washing afterward.
2. Metal Deposition: The metal is deposited by first depositing a barrier layer and then a metal layer.
Copper Plating & Outer-Layer Processing
There are two ways to deposit the outer layers of the laminates. We can apply the outer layers to both laminate surfaces or use them only on one surface. A double-sided copper process is helpful when applied to both surfaces. A single-sided copper process is useful when applied only to one surface.
“Double-Sided Copper” Process: (A) we tin-plate the PTH hole using an additive-free mix of tin/lead. We can do this in a dip tank or continuous plating line. Then we clean the substrate surface by a bright dip, and then the dielectric layer is deposited by electroless plating. Next, we deposit the conductive layer by electrolytic copper plating.
We solder the electrical leads to each substrate. The final is to inspect and test circuit design for functionality.
The process of lamination is ideal for a variety of biomedical applications. To produce alternating laminate patterns, we only coat one surface needs with copper. After placing the laminate in a vacuum furnace, we remove the excess copper by striping through a PTH plating process or via electropolishing.