RF PCB design layout and recommendations

1.RF transmission line


Many Maxim RF components require an controlled impedance transmission line that transmits RF power to (or transmits power from) IC pins on the PCB. These transmission lines can be implemented in the outer layer (top or bottom layer) or buried in the inner layer. Guidance on these transmission lines includes discussion of micro-strip lines, strip lines, co planar wave guides (ground), and characteristic impedance. It also introduces the transmission line corner compensation and the layer change of the transmission line.


RF PCB design layout


2.Micro-strip line


This type of transmission line includes fixed width metal traces (conductors) and ground planes directly below (adjacent layers). For example, traces on the first layer (top metal) require a solid grounded area on the second layer (Figure 1). The width of the trace, the thickness of the dielectric layer, and the type of dielectric determine the characteristic impedance (typically 50Ω or 75Ω)


Micro-strip line

1.Example of a micro-strip line (stereo view)


3.Strip line


Such a line includes a fixed width of the inner layer of the trace, and a grounded area above and below. The conductor can be located in the middle of the grounded area (Figure 2) or with a certain offset (Figure 3). This method is suitable for the inner layer of RF traces.


pcb Strip line

Figure 2. Strip-line (end view)



strip-line for PCBs

Figure 3. Offset strip-line. A variant of the strip-line for PCBs with different layer thicknesses (end view)


4.Coplanar waveguide (ground)


Coplanar waveguides provide better isolation (end view) between adjacent RF lines and other signal lines. This medium consists of an intermediate conductor and grounded areas on both sides and below (Figure 4).


adjacent RF lines

Figure 4. Coplanar waveguide provides better isolation between adjacent RF lines and other signal lines


It is recommended to install a via "fence" on both sides of the coplanar waveguide, as shown in Figure 5. This top view provides an example of installing a row of ground vias on the top metal ground area on each side of the intermediate conductor. The loop current caused on the top layer is shorted to the ground plane below.


coplanar waveguide

Figure 5. It is recommended to install a via fence on both sides of the coplanar waveguide.


Characteristic impedance There are a variety of calculation tools that can be used to correctly set the signal conductor line width to achieve the target impedance. However, care should be taken when entering the dielectric constant of the board layer. A typical PCB outer substrate layer contains a glass fiber component that is smaller than the inner layer, so the dielectric constant is low. For example, the dielectric constant of FR4 material is generally εR = 4.2, while the outer substrate (pre-cured) layer is generally εR = 3.8. The examples below are for reference only, where the metal thickness is 1 oz copper (1.4 mils, 0.036 mm).

Table 1. Example of characteristic impedance



5.Transmission line corner compensation


When the transmission line is required to bend (change direction) due to wiring constraints, the bending radius used should be at least 3 times the width of the intermediate conductor. That is:


Bending radius ≥ 3 × (line width)


This minimizes the characteristic impedance variation of the corners.

If it is not possible to achieve a gradual bend, the transmission line can be bent at a right angle (not curved), see Figure 6. However, this must be compensated to reduce the impedance jump caused by the increase in the local effective line width as it passes through the bend point. The standard compensation method is angle mitre, as shown in the figure below. The best microstrip right angle slanting is given by the Douville and James formula:



In the formula of Douville and James, M is the ratio (%) of the mitered and non-mitered corners. This formula is independent of the dielectric constant and is constrained by w/h ≥ 0.25.

A similar method can be used for other transmission lines. If there is any uncertainty about the correct compensation method and the design requires high performance transmission lines, the electromagnetic simulator should be used to model the corners.


bend the transmission line

Figure 6. If the gradual bending is not possible, bend the transmission line at right angles


6.Layer change of transmission line


If layout constraints require that the transmission line be changed to a different board layer, it is recommended to use at least two vias per transmission line to minimize the via inductive load. A pair of vias effectively reduces the transmission inductance by 50% and should use the largest diameter via that is equivalent to the transmission line width. For example, for a 15-mil microstrip line, the via diameter (polished plating diameter) should be 15 mils to 18 mils. If space is not allowed to use large vias, use three smaller transition vias.


7.Signal line isolation

Care must be taken to prevent accidental coupling between signal lines. The following are examples of potential coupling and preventive measures:


A.RF transmission line: The distance between transmission lines should be as large as possible and should not be close to each other over long distances. The smaller the spacing from each other, the longer the parallel trace distance, and the greater the coupling between the parallel microstrip lines. Traces on different layers should have grounded areas to keep them separate. Transmission lines carrying high power should be as far away as possible from other transmission lines. Grounded coplanar waveguides provide excellent line-to-line isolation. It is not practical to isolate the RF lines on a small RF PCB above about -45 dB.


B.High-speed digital signal lines: These signal lines should be placed independently on a different board layer than the RF signal lines to prevent coupling. Digital noise (from the clock, PLL, etc.) is coupled to the RF signal line and modulated onto the RF carrier. Or, in some cases, digital noise is upconverted/downconverted.


C.VCC/Power Cord: These wires should be placed on a dedicated layer. Appropriate decoupling/bypass capacitors should be installed at the primary VCC distribution node as well as the VCC branch. The bypass capacitor must be selected based on the overall frequency response of the RF IC and the expected frequency distribution of the digital noise caused by the clock and PLL. These traces should also be isolated from the RF line, which will emit large RF power.


8.Grounding area


If Layer 1 is used for RF components and transmission lines, it is recommended to use a solid (continuous) ground plane at Layer 2. For strip lines and offset strip lines, the grounding area is required for the upper and lower intermediate conductors. These areas must not be shared or assigned to a signal or power network, but must be allocated to the ground. Sometimes limited by design conditions, a local grounding area on a layer must be located below all RF components and transmission lines. The grounding area must not be disconnected below the transmission line.


A large number of ground vias should be placed between the different layers of the RF portion of the PCB. This helps prevent the ground current loop from causing an increase in parasitic ground inductance. Vias also help prevent cross-coupling of RF signal lines on the PCB from other signal lines.


9.Special considerations for power and ground planes


For board layers assigned to system power (DC power) and ground, the loop current of the component must be considered. The general principle is to avoid placing the signal lines on the board layer between the power plane and the ground plane.


signal layer between the power

Figure 7. Incorrect board layer assignment: There is a signal layer between the power plane and the ground current loop on the ground plane. Bias line noise is coupled to the signal layer


Better board layer assignment

Figure 8. Better board layer assignment: no signal layer between power pad and ground pad


10.Power (bias) trace and power supply decoupling


If the component has multiple power connections, it is common to use a "star" configuration of the power wiring (Figure 9). Install larger decoupling capacitors (tens of μF) at the “root” node of the star configuration and install smaller capacitors on each branch. The value of these small capacitors depends on the operating frequency of the RF IC and its specific function(decoupling between the stages and the mains). The figure below shows an example.


multiple power connections

Figure 9. If the component has multiple power connections, the power wiring can be star configured.


The "star" configuration avoids long ground loops relative to the configuration in which all pins connected to the same power network are connected in series. Long ground loops can cause parasitic inductance and can cause unexpected feedback loops. A key consideration in power supply decoupling is that the DC power connection must be electrically defined as an AC ground.