The LM5036 is a highly integrated half-bridge PWM controller that integrates an auxiliary bias supply to provide a high power density solution for telecom, datacom, and industrial power converters. The LM5036 includes all the functions required to implement a half-bridge topology power converter using voltage mode control. The device is suitable for the primary side of an isolated dc-to-dc converter with an input voltage of up to 100V. Compared to traditional half-bridge and full-bridge controllers, the LM5036 has its own irreplaceable advantages:
(1) Integrated auxiliary bias supply for powering the LM5036 and primary and secondary components without external auxiliary power, reducing board size and cost, enabling high power density and good thermal reliability.
(2) Enhanced pre-bias startup performance enables monotonically increasing the output voltage and avoiding sink current when the load is started.
(3) Improved cycle-by-cycle current limit through pulse matching to produce a uniform output current limit level over the input voltage range and also prevent transformer saturation.
Pulse-matched current limit protection mechanism
Constant current limiting problems and solutions:
During cycle-by-cycle operation, the CBC current limiting operation is activated when the current sense signal ISENSE reaches a positive threshold IPOS_LIM. The controller essentially exhibits peak current mode control with the voltage loop open during CBC operation. A common problem with peak current mode control is the subharmonic oscillation that occurs when the duty cycle of a half-bridge topology is greater than 0.25 (0.5 buck converter).
The rule of thumb is to add a compensation ramp whose slope must be set to at least half of the downhill slope of the output inductor current that is converted to the primary side by the current sense resistor. If you want to eliminate subharmonic oscillations after one switching cycle, you must set the slope compensation to double the slope of the output inductor current. This is called deadbeat control.
However, another problem arises after adding slope compensation. The current limit level varies with the input voltage as shown in the figure below. Due to the different slope compensation amplitudes at different input voltages, the actual current limit level varies with the input voltage given the internal current limit threshold. Such a mechanism makes the output current limiting tolerance poor. More design margin is required, resulting in poor power density.
The LM5036 ensures stable CBC operation by matching the number of tons of the primary MOSFET. The peak current limit threshold is adjusted by VIN to ensure that the output current limit varies with the input voltage. All of these features are set by three CS pins and associated external resistors. The values of these resistors can be calculated using the LM5036 design calculation table. Both positive and negative currents (causing the output voltage to drop or even be damaged) will be sensed and limited.
The LM5036 device has developed a new technology - input voltage compensation. By adding an additional signal as a function of the input voltage over the current sense signal and the slope compensation signal, the current limit value can be minimized over the entire input voltage range, resulting in a more accurate output power limit, maximally The threshold for avoiding output power varies with input voltage. In the LM5036 device, the slope compensation signal is the sawtooth current signal ISLOPE, which increases from 0 to 50μA (typical) at the oscillator frequency (twice the switching frequency).
The compensated current sense signal can now be derived as:
The left side of the figure below shows the external circuit of the LM5036 cycle-by-cycle current limit and the internal implementation of the LM5036.
The picture on the right shows the composition of the current sense signal. It can be seen that the LM5036 not only detects the forward current in the current detection, but also boosts the current sensed current value through the external RLIM resistor and the internal current source VLIM, thereby leaving a measurement space to sense the reverse current and set the reverse current threshold. At the same time, since the input voltage VIN signal is introduced to the current sensing, the sensing current contains input voltage information. This allows the current threshold to be kept within a small range over the entire voltage input range.
At the same time, the LM5036 has a pulse matching mechanism that maintains the flux balance of the main transformer during Cycle-By-Cycle operation. The duty ratios of the upper and lower main MOSFETs are always matched to ensure the balance of the voltage volt-seconds of the transformer, effectively preventing the transformer from saturating.
The pulse matching method is shown in the figure below. When the current limit is reached in the first phase, the FLAG signal inside the LM5036 goes from low to high. The RAMP signal is sampled on the rising edge of the FLAG signal and then remains at its original sample value for the next half of the high-side MOSFET phase. When the high-side phase RAMP signal rises above the sampled value, the high-side PWM pulse is turned off, which eventually causes the duty cycles of the two phases to match.
In over-current protection, the LM5036 and the conventional DC/DC control are both in the off-voltage control and enter the current control mode. However, in the current mode, the input voltage is introduced due to the addition of the ramp compensation. At this time, the upper limit of the conventional control will vary with the input voltage. However, in the LM5036, since the current detection also detects the input voltage value, the influence of the input voltage conversion can be effectively eliminated by internal control. At the same time, in the overcurrent protection, if the detection current reaches the threshold, the LM5036 can ensure the consistency of the turn-on time of the upper and lower tubes by pulse matching, thus avoiding the risk of transformer saturation.
The LM5306 can enter hiccup mode during overcurrent protection. Its period can be configured by an external capacitor on the RES pin. In addition to the traditional over-current snoring mode, the LM5036 also supports reverse current snoring mode protection. When the reverse current is repeated, the LM5036 can also enter the hiccup mode. Set a 15μA current source at the restart capacitor.
In the absence of a fully controllable pre-bias startup, the SR on the secondary side may close prematurely to sink current from the pre-charged output capacitor, passing it to the input, which results in a drop in capacitor voltage. If the voltage drop caused by this process is too large, it may cause the load to be restarted or even damage the power converter power stage. As can be seen from the figure below, there is a voltage drop and an overshoot in the output voltage during the startup without pre-bias adjustment.
The LM5036 features a new fully regulated pre-bias startup scheme to ensure monotonic rise in output voltage and avoid reverse current. The pre-bias startup process here mainly includes the primary side MOSFET and the secondary side SR soft start.
Pre-biased soft-start of the primary side FET (as shown in the system power-up sequence diagram in the following figure):
- The input voltage VIN rises with the rise of the externally applied voltage. Once VIN>15V and VCC/REF is higher than its UV threshold, the secondary side auxiliary power supply VAUX2 generated by Fly-buck will start. Here, in addition to providing power supply to the components on the secondary side, VAUX2 also participates as an enable signal in the pre-bias startup process.
- When the UVLO exceeds 1.25V and VCC/REF is above its UV threshold, the soft-start capacitor connected to the SS pin begins to charge. When SS < 2V, VAUX2 remains in the "off state". That is, VAUX2>threshold voltage TH (according to the design setting), at this time, a reset circuit that discharges the output voltage reference VREF is activated, thereby clamping the VREF value to ground. This ensures that the optocoupler produces a 0% duty cycle command. When UVLO exceeds 1.25V and VCC and REF are above the corresponding UV threshold, the soft-start capacitor begins to charge and the SS pin voltage begins to rise.
- When SS>=2V, the voltage value of VAUX2 enters the “on state” (VAUX2<TH, the voltage proportional relationship between “off state” and “on state” of VAUX2 is 1.4:1), and the auxiliary power source will generate the turn-on voltage. .
- When VAUX2<TH, VREF is clamped to ground and released, and the output voltage begins the soft start process. The duty cycle is controlled by the feedback loop and is not affected by the SS capacitor voltage (because Vcomp < Vss).
- When VREF>Vo (pre-bias voltage), Vcomp begins to rise.
- When Vcomp > 1V (corresponding to 0% duty cycle), the duty cycle of the primary FET begins to increase (Vo rises). At the same time, the synchronous rectification SR soft-start pin SSSR capacitor begins to charge.
Soft start process of the secondary side SR:
- Before SSSR>=1V, LM5036 works in SR SYNC mode, as shown in the following icon number 3. At this time, SR is completely synchronized with the main FET. The main functions are: 1) Help to reduce the conduction loss of SR; ) Avoid the risk of reverse currents.
- As the primary FET and SR pulse widths increase gradually, Vo gradually rises. This stepwise increase of the pulse width effectively prevents output voltage interference due to the difference in voltage drop between the body diode and SR Rdson.
- As the SSSR voltage rises, when SSSR > 1V, the LM5036 starts the soft start of the SR freewheeling period.
- SR1 and SR2 are simultaneously turned on during freewheeling.
- At the end of the SR freewheeling period, on the rising edge of the master clock, SR is related to the state of the main FET of the next power transfer period. The same phase continues to be opened, and the correlation is broken. (As shown in the figure below, SR1 and HSG are in phase-on, SR1 remains open at the rising edge of main clk on the 5th, and SR2 remains off due to out-of-phase, and the latter half is reversed.)
- At the end of the power transfer period, the main FET and the in-phase SR are turned off simultaneously. At the end of the soft start, the SR pulse will be complementary to the corresponding main FET.
Due to the secondary side pre-bias soft-start process, the secondary side reference voltage ramp can be effectively controlled, and the SR is activated only when the reference level VREF is higher than the output voltage. This ensures that the SR does not absorb the output capacitor energy during the entire startup process, and naturally there is no leakage of the capacitor voltage. As shown in the figure below, during the entire soft start process, the output voltage remains monotonously rising, which ensures that the digital circuits in the system start working in the correct order.
Please note that when designing a DC/DC converter with LM5036, the user does not need to consider this pre-bias startup process as this is a fully controlled function of the LM5036 itself.
Integrated auxiliary source:
For half-bridge drivers, the system requires a separate bias supply and more components when there is no external auxiliary supply. The secondary side bias voltage cannot be easily adjusted to control the system soft start process. Therefore, a separate external power supply and more components are required here, which will eventually occupy a large area of the board.
The LM5036 itself integrates a Fly-buck controller with a constant on-time control mode (COT) control mode that can be used to power the LM5036 and the primary and secondary side devices. Moreover, the length of the ON time in the COT control mode here can be set by the Ron of Pin-6. The voltage values of VAUX1 and VAUX2 can be set only by external RFB1 and RFB2. Only need to connect a small auxiliary source transformer, you can realize the LV5036 primary side VCC power supply, secondary side isolated drive power supply, isolated optocoupler op amp and other power supply (the power supply of each part shown in the above figure). VAUX2 also participates in the pre-bias startup process as a enable signal for communicating the primary side and the secondary side, and achieves the timing control of the pre-bias startup by cooperation with the discharge reset circuit. It can be seen that VAUX2 completes the primary side and secondary side communication here, avoiding the use of additional isolated signal circuits. Indirectly reduce the number of BOMs to increase power density. In addition, for the design of the auxiliary transformer, the design of the transformer and related devices can be realized through a simple tool design calculation table. The application is simple, and the board area and overall cost are greatly saved. As shown in the figure below, these functions can be easily realized by simply adding a small auxiliary transformer (yellow part), which greatly increases the system power density.
As shown in the figure above, SW_AUX is the output of Fly-buck, L3 is the output side inductance of buck circuit, C36 is the output side capacitance, R22 and R23 are feedback voltage dividing resistors, and R24, C34 and C35 form Type-3 ripple. Inject the circuit. When using the calculation tool, first input some basic information of the auxiliary power supply, frequency, load current value, and inductance value. The corresponding capacitor selection can be calculated.
For FB resistors, the corresponding FB resistors can be calculated from the voltages of the front and back stages of Flybuck, as shown in the Auxiliary Feedback Circuit table.
As for the parameter selection of the RCC ripple injection circuit, there are three different circuit selections in the calculation table. After selecting TYPE-3, the target ripple voltage value and the ripple current value can be input to calculate the corresponding RCC resistance value. . Here, the values of Cac and Rr are generally fixed, and Cr can be selected according to the calculated value.
The figure above shows the layout rules of the reference evaluation board based on LM5036. The upper part is the input filter circuit, half bridge circuit, output side synchronous rectification and output filter circuit. The lower part is the key components around the LM5036, the auxiliary power supply circuit and the feedback loop regulation circuit. The auxiliary power supply uses a very small footprint to achieve a multiplier effect. The 200W brick power supply commonly found in the industry usually uses 1/8 brick layout. Thanks to the high integration of the LM5036, the 200W power supply is now available on 1/16 brick modules, and the same power can be achieved on a smaller layout area.