Skip to content

How Many Common PCB Design Mistakes You Should Know

The PCB designing work is not an easy task but it is an art that involves many aspects from routing, placement, component selection, holes and vias placement. The PCB designer can make mistake during the PCB design layout but that mistake or error can be identified by a interactive tool that is supported by many CAD software like ALTIUM. This integrated tool is known as Design Rule Checker (DRC)

Design Rule Checker (DRC):

The purpose of the DRC is to cross check the PCB layout design against the capabilities/constraints of PCB fabrication shop. These constraints are communicated in terms of maximum tolerances to the PCB layout design engineer and the design engineer simply input these values to the DRC checker and Run DRC. As a result, any discrepancy is identified and rectified. The common constraints that DRC run can check are trace width, hole to trace clearance, overlaps, drill size, keep out, angle, blind via ratio and many others.

Design For Manufacturing (DFM):

On the other hand, Design for Manufacturing (DFM) is a tool that can cover the grey areas that are left (remain unidentified) by DRC. This DFM (unlike DRC which is not an Ad-on but an integrated tool of CAD software) is an Ad-on provided for additional cost as an extra service by PCB fabricators to the customer. This can ultimately raise the cost of PCB because of DFM dedicated software is expensive and require manpower training. The DFM check will result in more qualified, reliable and high yield end product PCB.

Now we will discuss some common design issues that may not be caught in DRC checker run. These are

1. Starved thermal pads

Starved thermal pads

It is commonly observed that when reworking on a PCB during de-soldering the component from PCB, it takes lot of time, heat and effort. This is because the copper is a good conductor of heat. So when applying heat from soldering iron, the heat is wasted through the copper pour into the copper plane because the pad is completely surrounded by copper. So the component pad does not get enough heat to melt the solder and remove the electronic component.

This issue is resolved by soldering the component on thermal pad. Thermal pad can have 2 or 4 thermal relief traces that connect the pad to the copper pour to copper plane.  The air gap reduces the contact area so heat is not dissipated/wasted.

Now the design issue occurs when the thermal relief traces is not properly connected to copper pour or plane. The reason is the close proximity of multiple vias / pads or small spacing in between vias / pads. These small space may be cleared by DRC checker, but in actual the thermal relief traces will disturb the effected via and can displace vias from its copper pour.

 vias / pads

2. Acid Traps Acute Angle

During the PCB design process, the design engineer can unknowingly makes a mistake. This mistake is that the two traces meet/cross each other at “acute angles” i.e less than 90O . As a result, the corners are made in the trace crossing point that can “trap” acid inside it. The acid referred here is the PCB etching solution used to etch away unwanted/excess copper from the PCB and only useful copper is left for making tracks/traces. This acid / etching solution is commonly available Ferric Chloride or Hydrochloric Acid.

The “acid trap hole” is another similar thing that arises due to very less gap between the trace and via. This will cause the space or pockets to form and retain the acid inside.

These acid if trapped for long time, can eat away copper trace and hence creates open circuit that can render the PCB board defective. The possibility of acid traps in multilayer PCB is very high. Recent advancement in etching method (photo activated etching solution) of PCB has made this issue trivial but still best practice must be ensure to avoid acute angle traces.

Acid Traps Acute Angle

3. Copper Pour with Narrow Trace:

In some cases, like SOIC-08 IC package, the pad pitch is 5 mil and let’s suppose the fabrication min spec is 10mil so it can short copper pour and pad as shown in the figure. In this figure the upper pour diagram shows the copper pour has width 0.005 inch while lower pour is 0.016 inch. And you can see that the lower pour is not present between the pads of SOIC. In Eagle Software this can be done by changing the copper pour width. This is the good practice as shown in lower pour and upper pour shown is a mistake that a PCB designer can make

If this mistake is made, this can result in breakage of this very thin 5 mil trace in little pieces which can float in other components of PCB to create short circuit.

Copper Pour with Narrow Trace:

4. Inadequate annular ring size

Inadequate annular ring size

The layers of PCB are interconnected by means of vias. The vias are made by drilling the holes on both sides and then plating the walls of holes thus interconnecting the inner layers and two external layers (sides) of PCB.

Now if the pad size is very small then the holes bored will take the large space on pad leaving very narrow or inadequate ring size. This is called annular ring. This insufficient annular ring is caused by inaccuracy in drill bit position and inaccuracy in hitting the target to drill holes .

annular ring

5. Via in Pads

Sometimes it is important for PCB designer to place a via in Pad of a component. This is done for sake of compact PCB routing. In traditional routing, DRC error can raise due to drill size and trace width etc. So for small pitch components like sub 0.5mm it is inevitable to use a via in Pad as shown in figure.

 Via in Pads

However the drawback of this is that this via will work as a straw that will suck the solder away from the pad and will cause the inadequate soldering of component upon the pad. The solution to this problem is to use “Capped Via” as shown in this figure. Filling the conductive epoxy is also good.

Capped Via

6. Copper Layer near the board edge

The copper can be brought just close to the edge of PCB board because the design engineer does not include the “keep out layer” or “outline layer” in the Gerber Files. This keep out layer is very important because if it is not included then the copper can be exposed  to air and can cause trouble when boards are panelized resulting in short circuiting the copper layers. This feature can be easily caught in both DRC and DFM.

Copper Layer near the board edge

7. Missing solder mask between pads

Missing solder mask between pads

Solder mask is also called solder resist. It is used to protect the solder away from the copper track that you do not want to solder. For example in very small pitch components like QFN package 0.4mm pitch it is nearly impossible to apply solder mask in this tight space so it is common that you will not find solder mask because of standard DRC rules. This will result in a problem of solder bridge as shown in figure.

solder mask

8. Tombstoning

During the PCB assembly, when the small SMT passive components being soldered, the Tombstoning is caused by the improper wetting. When the solder paste starts to melt, an imbalanced torque at the ends of the component terminals causes the component to lift from one end.  The component will be lifted from the end where the paste is wet. This Tombstoning can damage the PCB yields and raise cost of production. Other factors that cause Tombstoning are

1- Improper design of solder pads

2- Uneven solder paste printing

3- Uneven temperature of reflow oven

4- Placement of component parallel to reflow oven conveyer





                Get Fast Quote Now