1. Wiring width and current
The general width should not be less than 0.2mm (8mil)
On high-density, high-precision PCBs, the pitch and line width are typically 0.3mm (12mil).
When the thickness of the copper foil is about 50um, the wire width is 1~1.5mm (60mil) = 2A
The public place is generally 80mil, which is more important for applications with microprocessors.
2. How high is the high speed board?
When the rising/falling edge time of the signal is < 3~6 times the signal transmission time, it is considered as a high speed signal.
For digital circuits, the key is to look at the steepness of the edge of the signal, that is, the rise and fall times of the signal.
According to the theory of a very classic book “High Speed Digtal Design”, the signal rises from 10% to 90% less than 6 times the wire delay, which is a high-speed signal!—— That is, even a square wave of 8KHz The signal, as long as the edge is steep enough, is a high-speed signal, and the transmission line theory is needed for wiring.
3. PCB stacking and layering
（2） The wiring layer should be arranged adjacent to the image plane layer.
In order to have a better electromagnetic compatibility design, the multilayer printed board can meet the electromagnetic compatibility and sensitivity standards during normal operation. Proper stacking helps shield and suppress EMI. The following basic principles are generally followed in delamination and stacking of multilayer printed boards:
（3）Power and formation impedance are lowest.
（4）A strip line is formed in the middle layer, and a microstrip line is formed on the surface. The characteristics of the two are different.
（5） Important signal lines should be close to the ground.
A very important advantage of multi-layer boards over ordinary double-layer boards and single-layer boards is that signal lines and power supplies can be distributed on different board layers to improve signal isolation and anti-interference performance. However, many engineers still have headaches about the delamination and stacking of PCB, taking the commonly used 4-layer pcb board as an example.
The four-layer board has the following stacking sequences. The following explains the advantages and disadvantages of various stacks:
Note: S1 signal wiring layer, S2 signal wiring layer 2; GND ground layer POWER power layer
In the first case, it should be the best case of a four-layer board. Because the outer layer is the ground layer, it has a shielding effect on EMI, and the power layer is also reliable close to the ground layer, so that the internal resistance of the power source is small, and the best suburban fruit is obtained. However, the first case cannot be used when the density of the board is relatively large. Because of this, the integrity of the first layer cannot be guaranteed, and the second layer signal will become worse. In addition, this structure cannot be used in the case where the power consumption of the whole board is relatively large.
The second case is one of the most common ways we usually use. From the structure of the board, it is not suitable for high-speed digital circuit design. Because in this configuration, it is difficult to maintain a low power supply impedance. Take a plate of 2 mm as an example: Z0 = 50 ohms is required. The line width is 8 mils. The thickness of the copper foil is 35 цm. Thus the middle of the signal layer is 0.14mm between the ground and the ground. The formation and power layer are 1.58mm. This greatly increases the internal resistance of the power supply. In this structure, since the radiation is spatial, it is necessary to add a shield plate to reduce EMI.
In the third case, the signal line quality on the S1 layer is the best. S2 is second. It has a shielding effect on EMI. However, the power supply impedance is large. This board can be used when the power consumption of the whole board is large and the board is the source of interference or close to the source of interference.
4.pcb Impedance matching
The amplitude of the reflected voltage signal is determined by the source reflection coefficient ρs and the load reflection coefficient ρL.
ρL = (RL – Z0) / (RL + Z0) and ρS = (RS – Z0) / (RS + Z0)
In the above formula, if RL = Z0, the load reflection coefficient ρL = 0. If RS = Z0 source reflection coefficient ρS = 0.
Since the ordinary transmission line impedance Z0 should normally satisfy the 50 Ω requirement of about 50 Ω, the load impedance is usually in the range of several thousand ohms to several tens of kilo ohms. Therefore, it is difficult to achieve impedance matching on the load side. However, since the signal source (output) impedance is usually small, it is roughly a dozen ohms. Therefore, it is much easier to achieve impedance matching at the source. If the resistor is connected in parallel with the load, the resistor will absorb some of the signal and it will be unfavorable for transmission (I understand). When the TTL/CMOS standard 24mA drive current is selected, the output impedance is approximately 13Ω. If the transmission line impedance Z0 = 50Ω, then a 33Ω source termination resistor should be added. 13Ω+33Ω=46Ω (approx. 50Ω, weak underdamping contributes to signal setup time)
When other transmission standards and drive currents are selected, the matching impedance will vary. In high-speed logic and circuit design, for some key signals, such as clocks, control signals, etc., we recommend adding source-side matching resistors.
In this way, the signal is also reflected back from the load end. Because the source impedance matches, the reflected signal will not be reflected back.
5. Power cord and ground wire layout precautions
The power cord is as short as possible, straight, and it is best to go tree-shaped, do not walk the ring
Ground loop problem: For digital circuits, the ground loop caused by the ground loop is tens of millivolts, while the TTL anti-interference threshold is 1.2V, and the CMOS circuit can reach 1/2 supply voltage. That is to say, the ground loop circulation will not adversely affect the operation of the circuit. On the contrary, if the ground wire is not closed, the problem will be even bigger, because the pulse power supply current generated by the digital circuit will cause the ground potential imbalance at each point.
For example, I measured the ground current of the 74LS161 in reverse when the inverter is 1.2A. The 2Gsps oscilloscope measured the ground current pulse width of 7ns). Under the impact of large pulse current, if a distributed ground line (line width 25 mil) is used, the potential difference at each point between the ground lines will reach the level of 100 millivolts. After the ground loop is used, the pulse current is spread to various points of the ground line, which greatly reduces the possibility of interference with the circuit. With the closed ground wire, the maximum instantaneous potential difference of the ground of each device is measured to be one-half to one-fifth of the unclosed ground.
Of course, the measured data of boards with different densities and different speeds are very different. I said above, it refers to the level of the Z80 Demo board attached to the protel 99SE. For the low frequency analog circuit, I think the power frequency after the ground line is closed. Interference is sensed from space, which is not simulated or calculated anyway. If the ground wire is not closed, no ground eddy current will occur. Beckhamtao said, “But the ground wire is open, the power frequency induced voltage will be larger.” The theoretical basis and the two examples, I took over one of the others 7 years ago. The project, precision pressure gauge, uses a 14-bit A/D converter, but the actual measurement has only 11 effective precision.
After investigation, there is 15mVp-p power frequency interference on the ground. The solution is to simulate the ground loop of the PCB. Scratch, the front-end sensor to the A/D ground wire is distributed by the flying line. Later, the mass-produced model PCB is re-produced according to the flying line, and there has been no problem so far. The second example, a friend loves a fever, DIY a power amplifier, but the output always has a hum, I suggest it cut the ground loop, the problem is solved. Afterwards, this man reviewed dozens of “Hi-Fi machine” PCB diagrams, confirming that no machine used a ground loop in the analog part.
6. Printed circuit board design principles and anti-interference measures
A printed circuit board (PCB) is a support for circuit components and devices in an electronic product. It provides an electrical connection between the circuit components and the device. With the rapid development of electricity technology, the density of PGB is getting higher and higher. The quality of PCB design has a great influence on the interference capability. Therefore, in the PCB design, the general principles of PCB design must be observed and the requirements of anti-interference design should be met.
The principles of wiring are as follows:
(1) The wires used at the input and output terminals should be avoided as far as possible. It is best to add the ground wire between the wires to avoid feedback.
(2) The minimum width of the printed photoconductive wire is mainly determined by the adhesion strength between the wire and the insulating substrate and the current value flowing through them. When the thickness of the copper foil is 0.05mm and the width is 1 ~ 15mm, the current will not exceed 3 °C through the current of 2A. Therefore, the wire width of 1.5mm can meet the requirements. For integrated circuits, especially digital circuits, a wire width of 0.02 to 0.3 mm is usually selected. Of course, as long as it is allowed, use wide lines as much as possible, especially the power and ground lines. The minimum spacing of the wires is primarily determined by the worst case interline insulation resistance and breakdown voltage. For integrated circuits, especially digital circuits, the pitch can be as small as 5 to 8 mm as long as the process allows.
(3) The curved corner of the printed conductor generally takes a circular arc shape, and the right angle or angle affects the electrical performance in the high frequency circuit. In addition, try to avoid using large areas of copper foil, otherwise it will easily cause the copper foil to expand and fall off when heated for a long time. When a large area of copper foil is used, it is preferable to use a grid shape. This is advantageous in eliminating volatile gases generated by the heat of the adhesive between the copper foil and the pcb substrate.
The center hole of the pad is slightly larger than the diameter of the device lead. The pad is too large to form a solder joint. The pad outer diameter D is generally not less than (d + 1.2) mm, where d is the lead aperture. For high-density digital circuits, the minimum pad diameter can be (d + 1.0) mm.
PCB and circuit anti-interference measures
The anti-jamming design of printed circuit boards is closely related to the specific circuit. Here, only some common measures of PCB anti-interference design are explained.
9. Untwisting capacitor configuration
One of the usual practices in PCB design is to configure appropriate decoupling capacitors at various critical points in the printed board.
The general configuration principle for the untwisting capacitor is:
(1) The power input terminal is connected to an electrolytic capacitor of 10 ~ 100 uf. If possible, it is better to pick up 100uF or more.
(2) In principle, each integrated circuit chip should be equipped with a 0.01pF ceramic capacitor. If there is not enough space in the printed board, a capacitor of 1 ~ 10pF can be arranged every 4~8 chips.
(3) For devices with weak anti-noise capability and large power supply changes during shutdown, such as RAM and ROM storage devices, the decoupling capacitor should be directly connected between the power cable and the ground of the chip.
(4) The capacitor leads should not be too long, especially the high-frequency bypass capacitors must not have leads.
In addition, you should also pay attention to the following two points:
(1) When there are contacts, relays, buttons and other components in the printed board, a large spark discharge will occur when operating them, and the RC circuit shown in the drawing must be used to absorb the discharge current. Generally, R takes 1 ~ 2K and C takes 2.2 ~ 47UF.
(2) The input impedance of CMOS is very high and it is susceptible to induction. Therefore, it is necessary to ground or connect the power supply to the unused terminal during use.
10. Design tips and key points for efficient PCB automatic routing
Although the current EDA tools are very powerful, as PCB size requirements become smaller and the device density becomes higher and higher, PCB design is not difficult. How to achieve high PCB layout and shorten design time? This article introduces the design skills and key points of PCB planning, layout and wiring. Nowadays PCB design is getting shorter and shorter, smaller and smaller board space, higher device density, extremely harsh layout rules and large size components make the designer’s work more difficult. In order to solve the design difficulties and speed up the market launch, many manufacturers now prefer to use dedicated EDA tools to achieve PCB design.